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wan pll IDT82V3285 version 1 december 9, 2008 6024 silver creek valley road, san jose, ca 95138 telephone: (800) 345-7015 ? twx: 910-338-2070 ? fax: (408) 284-2775 printed in u.s.a. ? 2008 integrated device technology, inc.
disclaimer integrated device technology, inc. reserves the right to make changes to its products or specifications at any time, without no tice, in order to improve design or performance and to supply the best pos- sible product. idt does not assume any res ponsibility for use of any circuitry described other than the circuitry embodied in a n idt product. the company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent, pat ent rights or other rights, of integrated device technology, inc. life support policy integrated device technology's products ar e not authorized for use as critical com ponents in life support devices or systems un less a specific written agr eement pertaining to such intended use is exe- cuted between the manufacture r and an officer of idt. 1. life support devices or systems are devices or systems whic h (a) are intended for surgical implant into the body or (b) supp ort or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any components of a life support device or system whose fa ilure to perform can be reasonably expecte d to cause the failure of the life suppor t device or system, or to affect its safety or effectiveness.
table of contents 3 december 9, 2008 features ............. ................. ................ ................. .............. .............. .............. .............. ................. .............. .............. .......... 9 highlights..................................................................................................................... ............................................................................... 9 main features .................................................................................................................. .......................................................................... 9 other features ................................................................................................................. ........................................................................ 9 applications........... ................ ................. .............. .............. .............. ............... .............. .............. .............. .............. .......... 9 description............. ................ ................. .............. .............. .............. ............... ............. .................... ........... ............ ........ 10 functional block diagram ............... ................ ................. .............. .............. .............. ............. ............. ............ ........ 11 1 pin assignment ....... ................ ................. .............. .............. .............. ............... .............. ................ ................. ........... 12 2 pin description ........... ................ ................. ................ ................. ................ ................. ................ ................. ........... 13 3 functional description ............... ................ ................. .............. .............. .............. ............. ............. ............ ......... 18 3.1 reset ...................................................................................................................... ..................................................................................... 18 3.2 master clock ............................................................................................................... ........................................................................... 18 3.3 input clocks & fram e sync signal ........................................................................................... ...................................................... 19 3.3.1 input clocks ............................................................................................................. ....................................................................... 19 3.3.2 frame sync input signals ................................................................................................. ........................................................... 19 3.4 input clock pre-divider .................................................................................................... .................................................................. 20 3.5 input clock quality monitoring ............................................................................................. ........................................................ 21 3.5.1 activity monitoring ...................................................................................................... ................................................................... 21 3.5.2 frequency monitoring ..................................................................................................... .............................................................. 22 3.6 t0 / t4 dpll input clock selection ......................................................................................... ......................................................... 23 3.6.1 external fast selection (t0 only) ........................................................................................ .......................................................... 23 3.6.2 forced selection ......................................................................................................... ................................................................... 24 3.6.3 automatic selection ...................................................................................................... ................................................................. 24 3.7 selected input clock monitoring ............................................................................................ ...................................................... 25 3.7.1 t0 / t4 dpll locking detection ........................................................................................... ........................................................ 25 3.7.1.1 fast loss .............................................................................................................. ............................................................ 25 3.7.1.2 coarse phase loss ...................................................................................................... .................................................... 25 3.7.1.3 fine phase loss ........................................................................................................ ....................................................... 25 3.7.1.4 hard limit exceeding ................................................................................................... .................................................... 25 3.7.2 locking status ........................................................................................................... .................................................................... 25 3.7.3 phase lock alarm (t0 only) ............................................................................................... ........................................................... 26 3.8 selected input clock switch ................................................................................................ ........................................................... 27 3.8.1 input clock validity ..................................................................................................... ................................................................... 27 3.8.2 selected input clock switch .............................................................................................. ........................................................... 27 3.8.2.1 revertive switch ....................................................................................................... ........................................................ 27 3.8.2.2 non-revertive switch (t0 only) ......................................................................................... ............................................... 28 3.8.3 selected / qualified input clocks indication ............................................................................. ................................................... 28 3.9 selected input clock status vs. dpll operating mode ........................................................................ ............................... 29 3.9.1 t0 selected input clock vs. dpll operating mode .......................................................................... .......................................... 29 3.9.2 t4 selected input clock vs. dpll operating mode .......................................................................... .......................................... 31 3.10 t0 / t4 dpll operating mode ............................................................................................... ................................................................ 32 3.10.1 t0 dpll operating mode .................................................................................................. ............................................................ 32 3.10.1.1 free-run mode ......................................................................................................... ....................................................... 32 3.10.1.2 pre-locked mode ....................................................................................................... ...................................................... 32 3.10.1.3 locked mode ........................................................................................................... ......................................................... 32 3.10.1.3.1 temp-holdover mode .................................................................................................. .................................. 32 table of contents
table of contents 4 december 9, 2008 IDT82V3285 wan pl l 3.10.1.4 lost-phase mode ....................................................................................................... ...................................................... 32 3.10.1.5 holdover mode ......................................................................................................... ........................................................ 32 3.10.1.5.1 automatic instantaneous ............................................................................................. .................................. 33 3.10.1.5.2 automatic slow averaged ............................................................................................. ................................ 33 3.10.1.5.3 automatic fast averaged ............................................................................................. ................................. 33 3.10.1.5.4 manual .............................................................................................................. ............................................. 33 3.10.1.5.5 holdover frequency offset read ...................................................................................... ............................ 33 3.10.1.6 pre-locked2 mode ...................................................................................................... ..................................................... 33 3.10.2 t4 dpll operating mode .................................................................................................. ............................................................ 33 3.10.2.1 free-run mode ......................................................................................................... ....................................................... 33 3.10.2.2 locked mode ........................................................................................................... ......................................................... 33 3.10.2.3 holdover mode ......................................................................................................... ........................................................ 33 3.11 t0 / t4 dpll output ....................................................................................................... .......................................................................... 35 3.11.1 pfd output limit ........................................................................................................ .................................................................... 35 3.11.2 frequency offset limit .................................................................................................. ................................................................ 35 3.11.3 pbo (t0 only) ........................................................................................................... ...................................................................... 35 3.11.4 phase offset selection (t0 only) ........................................................................................ .......................................................... 35 3.11.5 four paths of t0 / t4 dpll outputs ...................................................................................... ....................................................... 35 3.11.5.1 t0 path ............................................................................................................... .............................................................. 35 3.11.5.2 t4 path ............................................................................................................... .............................................................. 36 3.12 t0 / t4 apll .............................................................................................................. ................................................................................... 37 3.13 output clocks & frame sync signals ........................................................................................ ................................................... 37 3.13.1 output clocks ........................................................................................................... ...................................................................... 37 3.13.2 frame sync output signals ............................................................................................... .......................................................... 39 3.14 master / slave configuration .............................................................................................. ........................................................... 41 3.15 interrupt summary ......................................................................................................... ...................................................................... 42 3.16 t0 and t4 summary ......................................................................................................... ........................................................................ 42 3.17 power supply filtering techniques ......................................................................................... .................................................... 43 4 typical application ......... ................ ................. ................ ................. ................ ............... .............. .............. ........... 44 4.1 master / slave application ................................................................................................. .............................................................. 44 5 microprocessor interface ............. ................ ................. .............. .............. .............. ............. ............... .............. 45 5.1 eprom mode ................................................................................................................. ............................................................................. 46 5.2 multiplexed mode ........................................................................................................... ....................................................................... 47 5.3 intel mode ................................................................................................................. ................................................................................ 49 5.4 motorola mode .............................................................................................................. ........................................................................ 51 5.5 serial mode ................................................................................................................ .............................................................................. 53 6 jtag ........... ................. ................ ................. ................ ................. .............. ............. ............... ............... .............. ........... 55 7 programming information ... ................ ................. ................ ................. ................ ................. ................ .............. 56 7.1 register map ............................................................................................................... ............................................................................. 56 7.2 register description ....................................................................................................... .................................................................... 61 7.2.1 global control registers ................................................................................................. .............................................................. 61 7.2.2 interrupt registers ...................................................................................................... ................................................................... 70 7.2.3 input clock frequency & prio rity configuration registers ................................................................. ...................................... 74 7.2.4 input clock quality monitoring configuration & status registers .......................................................... ................................. 85 7.2.5 t0 / t4 dpll input clock selection registers ............................................................................. ................................................ 96 7.2.6 t0 / t4 dpll state m achine control registers ............................................................................. ............................................ 101 7.2.7 t0 / t4 dpll & apll configuration registers .............................................................................. ............................................ 103 7.2.8 output configuration registers ........................................................................................... ....................................................... 117 7.2.9 pbo & phase offset control registers ..................................................................................... ................................................. 124 7.2.10 synchronization configuration registers ................................................................................. ................................................ 126 8 thermal management ......... ................. ................ ................. ................. ................ ............... ........... ............ ......... 127 8.1 junction temperature ....................................................................................................... ............................................................... 127 8.2 example of junction temperature calculation ................................................................................ ................................... 127
table of contents 5 december 9, 2008 IDT82V3285 wan pl l 8.3 heatsink evaluation ........................................................................................................ .................................................................. 127 8.4 tqfp epad thermal release path ............................................................................................. .................................................... 128 9 electrical specifications ............ ................. .............. .............. .............. .............. ............... ................ .............. 129 9.1 absolute maximum rating .................................................................................................... ............................................................ 129 9.2 recommended operation conditions ........................................................................................... ............................................... 129 9.3 i/o specifications ......................................................................................................... ........................................................................ 130 9.3.1 cmos input / output port ................................................................................................. ........................................................... 130 9.3.2 pecl / lvds input / output port .......................................................................................... ...................................................... 131 9.3.2.1 pecl input / output port ............................................................................................... ................................................. 131 9.3.2.2 lvds input / output port ............................................................................................... ................................................. 133 9.4 jitter & wander performance ................................................................................................ ....................................................... 134 9.5 output wander generation ................................................................................................... ......................................................... 137 9.6 input / output clock timing ................................................................................................ ............................................................. 138 9.7 output clock timing ........................................................................................................ ................................................................... 139 package dimensions............ ................. ................ ................. ................ ................. .............. .............. .............. ........... 144 ordering information........ ................. ................ ................. ................ ................. ................ ............... .............. ........ 147
list of tables 6 december 9, 2008 table 1: pin description ..................................................................................................... ........................................................................................ 13 table 2: related bit / register in chapter 3.2 ................................................................................ ........................................................................... 18 table 3: related bit / register in chapter 3.3 ................................................................................ ........................................................................... 19 table 4: related bit / register in chapter 3.4 ................................................................................ ........................................................................... 20 table 5: related bit / register in chapter 3.5 ................................................................................ ........................................................................... 22 table 6: input clock selection for t0 path ................................................................................... ............................................................................. 23 table 7: input clock selection for t4 path ................................................................................... ............................................................................. 23 table 8: external fast selection ............................................................................................. ................................................................................... 23 table 9: related bit / register in chapter 3.6 ................................................................................ ........................................................................... 24 table 10: coarse phase limit pr ogramming (the selected input clock of 2 khz, 4 khz or 8 khz) ................................. ............................................. 25 table 11: coarse phase limit progr amming (the selected input clock of ot her than 2 khz, 4 khz and 8 khz) ..................... ..................................... 25 table 12: related bit / register in chapter 3.7 ............................................................................... ............................................................................ 26 table 13: conditions of qualified input cl ocks available for t0 & t4 selection ............................................... .......................................................... 27 table 14: related bit / register in chapter 3.8 ............................................................................... ............................................................................ 28 table 15: t0 dpll operating mode control ..................................................................................... .......................................................................... 29 table 16: t4 dpll operating mode control ..................................................................................... .......................................................................... 31 table 17: related bit / register in chapter 3.9 ............................................................................... ............................................................................ 31 table 18: frequency offset control in temp-holdover mode ..................................................................... ................................................................ 32 table 19: frequency offset control in holdover mode .......................................................................... ..................................................................... 33 table 20: holdover frequency offset read ..................................................................................... ........................................................................... 33 table 21: related bit / register in chapter 3.10 .............................................................................. ........................................................................... 34 table 22: related bit / register in chapter 3.11 .............................................................................. ........................................................................... 36 table 23: related bit / register in chapter 3.12 .............................................................................. ........................................................................... 37 table 24: outputs on out1 ~ out5 if derived from t0/t4 dpll outputs .......................................................... ...................................................... 37 table 25: outputs on out1 ~ out5 if derived from t0/t4 apll .................................................................. ............................................................ 38 table 26: synchronization control ............................................................................................ ................................................................................... 39 table 27: related bit / register in chapter 3.13 .............................................................................. ........................................................................... 40 table 28: device master / slave control ...................................................................................... ............................................................................... 41 table 29: related bit / register in chapter 3.15 .............................................................................. ........................................................................... 42 table 30: microprocessor interface ........................................................................................... .................................................................................. 45 table 31: access timing charac teristics in eprom mode ........................................................................ ................................................................. 46 table 32: read timing characterist ics in multiplexed mode .................................................................... ................................................................... 47 table 33: write timing characteri stics in multiplexed mode ................................................................... .................................................................... 48 table 34: read timing characte ristics in intel mode .......................................................................... ........................................................................ 49 table 35: write timing charac teristics in intel mode ......................................................................... ......................................................................... 50 table 36: read timing characteri stics in motorola mode ....................................................................... .................................................................... 51 table 37: write timing characte ristics in motorola mode ...................................................................... ..................................................................... 52 table 38: read timing characte ristics in serial mode ......................................................................... ....................................................................... 53 table 39: write timing characte ristics in serial mode ........................................................................ ........................................................................ 54 table 40: jtag timing characteristics ........................................................................................ ............................................................................... 55 table 41: register list and map .............................................................................................. .................................................................................... 56 table 42: power consumption and maximum junction temperature ................................................................. ...................................................... 127 table 43: thermal data ....................................................................................................... ...................................................................................... 127 table 44: absolute maximum rating ............................................................................................ ............................................................................. 129 table 45: recommended operation conditions ................................................................................... ..................................................................... 129 table 46: cmos input port electrical characteristics ......................................................................... ...................................................................... 130 table 47: cmos input port with internal pu ll-up resistor electric al characteristics .......................................... ...................................................... 130 table 48: cmos input port with internal pull -down resistor electric al characteristics ........................................ ................................................... 130 list of tables
list of tables 7 december 9, 2008 IDT82V3285 wan pl l table 49: cmos output port el ectrical characteristics ........................................................................ .................................................................... 130 table 50: pecl input / output port electrical characteristics ................................................................ ................................................................... 132 table 51: lvds input / output port electrical characteristics ................................................................ ................................................................... 133 table 52: output clock jitter generation ..................................................................................... ............................................................................. 134 table 53: output clock phase noise ........................................................................................... .............................................................................. 135 table 54: input jitter tolerance (155.52 mhz) ................................................................................ .......................................................................... 135 table 55: input jitter tolerance (1.544 mhz) ................................................................................. ........................................................................... 135 table 56: input jitter tolerance (2.048 mhz) ................................................................................. ........................................................................... 135 table 57: input jitter tolerance (8 khz) ..................................................................................... ............................................................................... 135 table 58: t0 dpll jitter transfer & damping factor ........................................................................... .................................................................... 136 table 59: t4 dpll jitter transfer & damping factor ........................................................................... .................................................................... 136 table 60: input/output clock timing 3 ........................................................................................ .............................................................................. 138 table 61: output clock timing ................................................................................................ .................................................................................. 139
list of figures 8 december 9, 2008 figure 1. functional block diagram ........................................................................................... ................................................................................. 11 figure 2. pin assignment (top view) .......................................................................................... ................................................................................ 12 figure 3. pre-divider for an input clock ..................................................................................... ................................................................................ 20 figure 4. input clock activity monitoring .................................................................................... ................................................................................. 21 figure 5. external fast selection ............................................................................................ .................................................................................... 23 figure 6. qualified input clocks for automatic selection ..................................................................... ....................................................................... 24 figure 7. t0 selected input clock vs. dpll automatic operating mode .......................................................... ......................................................... 30 figure 8. t4 selected input clock vs. dpll automatic operating mode .......................................................... ......................................................... 31 figure 9. on target frame sync input signal timing ........................................................................... ...................................................................... 39 figure 10. 0.5 ui early frame sync input signal timing ....................................................................... ...................................................................... 39 figure 11. 0.5 ui late frame sync input signal timing ........................................................................ ...................................................................... 40 figure 12. 1 ui late frame sync input signal timing .......................................................................... ....................................................................... 40 figure 13. physical connecti on between two devices ........................................................................... ................................................................... 41 figure 14. IDT82V3285 power decoupling scheme ................................................................................ ................................................................... 43 figure 15. typical application ............................................................................................... ....................................................................................... 44 figure 16. eprom acce ss timing diagram ....................................................................................... ........................................................................ 46 figure 17. multiplexed read timing diagram ................................................................................... .......................................................................... 47 figure 18. multiplexed write timing diagram .................................................................................. ............................................................................ 48 figure 19. intel read timing diagram ......................................................................................... ................................................................................ 49 figure 20. intel write timing diagram ........................................................................................ ................................................................................. 50 figure 21. motorola read timing diagram ...................................................................................... ............................................................................ 51 figure 22. motorola wr ite timing diagram ..................................................................................... ............................................................................. 52 figure 23. serial read timing di agram (clke asserted low) .................................................................... ............................................................... 53 figure 24. serial read timing diagram (clke asserted high) ................................................................... ............................................................... 53 figure 25. serial write timing diagram ....................................................................................... ................................................................................ 54 figure 26. jtag interface timing diagram ..................................................................................... ............................................................................ 55 figure 27. assembly for expose pad thermal release path (side view) .......................................................... ....................................................... 128 figure 28. recommended pecl input port line termination ...................................................................... ............................................................ 131 figure 29. recommended pecl out put port line termination ..................................................................... ........................................................... 131 figure 30. recommended lvds input port line termination ...................................................................... ............................................................ 133 figure 31. recommended lvds out put port line termination ..................................................................... ........................................................... 133 figure 32. output wander generation .......................................................................................... ............................................................................ 137 figure 33. input / output clock timing ....................................................................................... ............................................................................... 138 figure 34. output clock timing ............................................................................................... .................................................................................. 139 figure 35. 100-pin eqg package dim ensions (a) (in millimeters) ............................................................... ............................................................. 144 figure 36. 100-pin eqg package dim ensions (b) (in millimeters) ............................................................... ............................................................. 145 figure 37. eqg100 recommended land pattern with exposed pad (in millimeters) ................................................. ............................................. 146 list of figures
9 december 9, 2008 IDT82V3285 ? 2008 integrated device technology, inc. dsc-6988/1 wan pll idt and the idt logo are trademarks of integrated device technology, inc. features highlights ? the first single pll chip: ? features 0.5 mhz to 560 hz bandwidth ? exceeds gr-253-core (oc-12) and itu-t g.813 (stm-16/ option i) jitter generation requirements ? provides node clocks for cellul ar and wll base-station (gsm and 3g networks) ? provides clocks for dsl access concentrators (dslam), espe- cially for japan tcm-isdn netwo rk timing based adsl equip- ments main features ? provides an integrated single-chip solution for synchronous equip- ment timing source, including stratum 2, 3e, 3, smc, 4e and 4 clocks ? employs dpll and apll to feature excellent jitter performance and minimize the number of the external components ? integrates t0 dpll and t4 dpll; t4 dpll locks independently or locks to t0 dpll ? supports forced or automatic ope rating mode switch controlled by an internal state machine; the primary operating modes are free- run, locked and holdover ? supports programmable dpll bandwidth (0.5 mhz to 560 hz in 19 steps) and damping factor (1.2 to 20 in 5 steps) ? supports 1.1x10 -5 ppm absolute holdover accuracy and 4.4x10 -8 ppm instantaneous holdover accuracy ? supports pbo to minimize phase transients on t0 dpll output to be no more than 0.61 ns ? supports phase absorption w hen phase-time changes on t0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds ? supports programmable input-to- output phase offset adjustment ? limits the phase and frequency offset of the outputs ? supports manual and automatic selected input clock switch ? supports automatic hitless selected input clock switch on clock fail- ure ? supports three types of input clo ck sources: recovered clock from stm-n or oc-n, pdh network sy nchronization timing and external synchronization reference timing ? provides a 2 khz, 4 khz or 8 kh z frame sync input signal, and a 2 khz and an 8 khz frame sync output signals ? provides 5 input clocks whos e frequency cover from 2 khz to 622.08 mhz ? provides 5 output clocks whos e frequency cover from 1 hz to 622.08 mhz ? provides output clocks for bits, gps, 3g, gsm, etc. ? supports pecl/lvds and cmos input/output technologies ? supports master clock calibration ? supports master/slave applicati on (two chips used together) to enable system protection against single chip failure ? meets telcordia gr-1244-co re, gr-253-core, gr-1377- core, itu-t g.812, itu-t g.813 and itu-t g.783 criteria other features ? multiple microprocessor interf ace modes: eprom, multiplexed, intel, motorola and serial ? ieee 1149.1 jtag boundary scan ? single 3.3 v operation with 5 v tolerant cmos i/os ? 100-pin tqfp package, green package options available applications ? bits / ssu ? smc / sec (sonet / sdh) ? dwdm cross-connect and transmission equipments ? central office timing source and distribution ? core and access ip switches / routers ? gigabit and terabit ip switches / routers ? ip and atm core switches and access equipments ? cellular and wll base-station node clocks ? broadband and multi-service access equipments ? any other telecom equipments that need synchronous equipment system timing
IDT82V3285 wan pl l description 10 december 9, 2008 description the IDT82V3285 is an integrated, single-chip solution for the syn- chronous equipment timing source for stratum 2, 3e, 3, smc, 4e and 4 clocks in sonet / sdh equipments, dwdm and wireless base station, such as gsm, 3g, dsl concentrator, router and access network appli- cations. the device supports three types of input clock sources: recovered clock from stm-n or oc-n, pdh network synchronization timing and external synchronization reference timing. based on itu-t g.783 and telcordi a gr-253-core, the device con- sists of t0 and t4 paths. the t0 path is a high quality and highly config- urable path to provide system cl ock for node timing synchronization within a sonet / sdh network. the t4 path is simpler and less config- urable for equipment synchronizati on. the t4 path locks independently from the t0 path or locks to the t0 path. an input clock is automatically or manually selected for t0 and t4 each for dpll locking. both the t0 and t4 paths support three primary operating modes: free-run, locked and holdover. in free-run mode, the dpll refers to the master clock. in locked mode, the dpll locks to the selected input clock. in holdover mode, the dpll resorts to the fre- quency data acquired in locked mode. whatever the operating mode is, the dpll gives a stable performance without being affected by operat- ing conditions or silic on process variations. if the dpll outputs are processed by t0/t4 apll, the outputs of the device will be in a better jitter/wander performance. the device provides programma ble dpll bandwidths: 0.5 mhz to 560 hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. different settings cover all sonet / sdh cl ock synchronization requirements. a high stable input is required for t he master clock in different appli- cations. the master clock is used as a reference clock for all the internal circuits in the device. it can be calibrated within 741 ppm. all the read/write registers are accessed through a microprocessor interface. the device supports fi ve microprocessor interface modes: eprom, multiplexed, intel, motorola and serial. in general, the device can be used in master/slave application. in this application, two devices s hould be used together to enable system protection against single chip failure. see chapter 4 typical application for details.
IDT82V3285 wan pl l functional block diagram 11 december 9, 2008 functional block diagram figure 1. functional block diagram ex_sync1 monitors t0 pfd & lpf divider t4 pfd & lpf divider apll microprocessor interface jtag pbo phase offset 77.76 mhz t4 apll t0 apll divider out1 out1 mux divider out2 out2 mux out3 out4 out4 mux out5 out5 mux out3 mux mux t4 apll mux t0 apll mux t4 input selector t0 input selector osci 77.76 mhz 16e1/16t1 12e1/24t1/e3/t3 16e1/16t1 12e1/24t1/e3/t3 auto divider auto divider 10 10 10 10 10 t0 dpll t4 dpll selection input in1 in2 in3 in4 in5 frsync_8k mfrsync_2k output gsm/gps/16e1/16t1 t0 77.76 mhz t0 8 khz gsm/obsai/16e1/16t1 8 k divider input pre-divider priority input pre-divider priority input pre-divider priority input pre-divider priority input pre-divider priority divider divider divider
IDT82V3285 wan pl l pin assignment 12 december 9, 2008 1 pin assignment figure 2. pin assignment (top view) IDT82V3285 agnd trst ic1 ic2 agnd1 vdda1 tms int_req tck osci dgnd1 vddd1 vddd3 dgnd3 dgnd2 vddd2 ic3 ff_srcsw vdda2 agnd2 tdo ic4 tdi nc nc rdy rst ale/sclk rd wr cs a0/sdi a1/clke a2 a3 a4 a5 a6 dgnd5 vddd5 mpu_mode0 mpu_mode1 mpu_mode2 nc nc nc in5 nc nc nc vddd8 nc nc dgnd8 frsync_8k m frsync_2k gnd_diff1 vdd_diff1 out4_pos out4_neg out5_pos out5_neg gnd_diff2 vdd_diff2 in3_pos in3_neg in4_pos in4_neg nc ex_sync1 in1 in2 nc dgnd4 vddd4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 sonet/ sdh ms/ sl ic7 ic6 ic5 nc out3 out2 agnd3 vdda3 out1 nc nc dgnd7 vddd7 vddd6 dgnd6 ad0/sdo ad1 ad2 ad3 ad4 ad5 ad6 ad7
IDT82V3285 wan pl l pin description 13 december 9, 2008 2 pin description table 1: pin description name pin no. i/o type description 1 global control signal osci 10 i cmos osci: crystal oscillator master clock a nominal 12.8000 mhz clock provided by a crystal oscillator is input on this pin. it is the master clock for the device. ff_srcsw 18 i pull-down cmos ff_srcsw: external fast selection enable during reset, this pin determines the default value of the ext_sw bit (b4, 0bh) 2 . the ext_sw bit determines whether the external fast selection is enabled. high: the default value of the ext_sw bit (b4, 0bh) is ?1? (external fast selection is enabled); low: the default value of the ext_sw bit (b4, 0bh) is ?0? (external fast selection is dis- abled). after reset, this pin selects an input clock pair for the t0 dpll if the external fast selection is enabled: high: pair in1 / in3 is selected. low: pair in2/ in4 is selected. after reset, the input on this pin takes no effect if the external fast selection is disabled. ms/ sl 99 i pull-up cmos ms/ sl : master / slave selection this pin, together with the ms_sl_ctrl bit (b0, 13h), controls whether the device is config- ured as the master or as the slave. refer to chapter 3.14 master / slave configuration for details. the signal level on this pin is reflected by the master_slave bit (b1, 09h). sonet/ sdh 100 i pull-down cmos sonet/ sdh : sonet / sdh frequency selection during reset, this pin determines the default value of the in_sonet_sdh bit (b2, 09h): high: the default value of the in_sonet_sdh bit is ?1? (sonet); low: the default value of the in_sonet_sdh bit is ?0? (sdh). after reset, the value on this pin takes no effect. rst 74 i pull-up cmos rst : reset a low pulse of at least 50 s on this pin resets the device. after this pin is high, the device will still be held in reset state for 500 ms (typical). frame synchronization input signal ex_sync1 45 i pull-down cmos ex_sync1: external sync input 1 a 2 khz, 4 khz or 8 khz signal is input on this pin. input clock in1 46 i pull-down cmos in1: input clock 1 a 2 khz, 4 khz, n x 8 khz 3 , 1.544 mhz (sonet) / 2.048 mhz (sdh), 6.48 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz or 155.52 mhz clock is input on this pin. in2 47 i pull-down cmos in2: input clock 2 a 2 khz, 4 khz, n x 8 khz 3 , 1.544 mhz (sonet) / 2.048 mhz (sdh), 6.48 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz or 155.52 mhz clock is input on this pin. in3_pos in3_neg 40 41 i pecl/lvds in3_pos / in3_neg: positive / negative input clock 3 a 2 khz, 4 khz, n x 8 khz 3 , 1.544 mhz (sonet) / 2.048 mhz (sdh), 6.48 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mh z, 155.52 mhz, 311.04 mhz or 622.08 mhz clock is differentially input on this pair of pins. whether the clock signal is pecl or lvds is automatically detected. in4_pos in4_neg 42 43 i pecl/lvds in4_pos / in4_neg: positive / negative input clock 4 a 2 khz, 4 khz, n x 8 khz 3 , 1.544 mhz (sonet) / 2.048 mhz (sdh), 6.48 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mh z, 155.52 mhz, 311.04 mhz or 622.08 mhz clock is differentially input on this pair of pins. whether the clock signal is pecl or lvds is automatically detected.
IDT82V3285 wan pl l pin description 14 december 9, 2008 in5 54 i pull-down cmos in5: input clock 5 a 2 khz, 4 khz, n x 8 khz 3 , 1.544 mhz (sonet) / 2.048 mhz (sdh), 6.48 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz or 155.52 mhz clock is input on this pin. in slave operation, the frequency of the t0 selected input clock in5 is recommended to be 6.48 mhz. output frame synchronization signal frsync_8k 30 o cmos frsync_8k: 8 khz frame sync output an 8 khz signal is output on this pin. mfrsync_2k 31 o cmos mfrsync_2k: 2 khz multiframe sync output a 2 khz signal is output on this pin. output clock out1 90 o cmos out1: output clock 1 a 1 hz, 400 hz, 2 khz, 8 khz, 64 khz, n x e1 4 , n x t1 5 , n x 13.0 mhz 6 , n x 3.84 mhz 7 , 5 mhz, 10 mhz, 20 mhz, e3, t3, 6.48 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz or 155.52 mhz clock is output on this pin. out2 93 o cmos out2: output clock 2 a 1 hz, 400 hz, 2 khz, 8 khz, 64 khz, n x e1 4 , n x t1 5 , n x 13.0 mhz 6 , n x 3.84 mhz 7 , 5 mhz, 10 mhz, 20 mhz, e3, t3, 6.48 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz or 155.52 mhz clock is output on this pin. out3 94 o cmos out3: output clock 3 a 1 hz, 400 hz, 2 khz, 8 khz, 64 khz, n x e1 4 , n x t1 5 , n x 13.0 mhz 6 , n x 3.84 mhz 7 , 5 mhz, 10 mhz, 20 mhz, e3, t3, 6.48 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz or 155.52 mhz clock is output on this pin. out4_pos out4_neg 34 35 o pecl/lvds out4_pos / out4_neg: positive / negative output clock 4 a 1 hz, 400 hz, 2 khz, 8 khz, 64 khz, n x e1 4 , n x t1 5 , n x 13.0 mhz 6 , n x 3.84 mhz 7 , 5 mhz, 10 mhz, 20 mhz, e3, t3, 6.48 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz, 155.52 mhz, 311.04 mhz or 622.08 mhz clock is differentially output on this pair of pins. out5_pos out5_neg 36 37 o pecl/lvds out5_pos / out5_neg: positive / negative output clock 5 a 1 hz, 400 hz, 2 khz, 8 khz, 64 khz, n x e1 4 , n x t1 5 , n x 13.0 mhz 6 , n x 3.84 mhz 7 , 5 mhz, 10 mhz, 20 mhz, e3, t3, 6.48 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz, 155.52 mhz, 311.04 mhz or 622.08 mhz clock is differentially output on this pair of pins. microprocessor interface cs 70 i pull-up cmos cs : chip selection a transition from high to low must occur on this pin for each read or write operation and this pin should remain low until the operation is over. int_req 8 o cmos int_req: interrupt request this pin is used as an interrupt request. the output characteristics are determined by the hz_en bit (b1, 0ch) and the int_pol bit (b0, 0ch). table 1: pin description (continued) name pin no. i/o type description 1
IDT82V3285 wan pl l pin description 15 december 9, 2008 mpu_mode0 mpu_mode1 mpu_mode2 60 59 58 i pull-down cmos mpu_mode[2:0]: microprocessor interface mode selection the device supports five microprocessor interface modes: eprom, multiplexed, intel, motor- ola and serial. during reset, these pins determine the default value of the mpu_sel_cnfg[2:0] bits (b2~0, 7fh) as follows: 001 (eprom mode); 010 (multiplexed mode); 011 (intel mode); 100 (motorola mode); 101 (serial mode); 110 - 111 (reserved). after reset, these pins are general purpose inputs. the microprocessor interface mode is selected by the mpu_sel_cnfg[2:0] bits (b2~0, 7fh). the value of these pins is always reflected by the mpu_pin_sts[2:0] bits (b2~0, 02h). a0 / sdi a1 / clke a2 a3 a4 a5 a6 69 68 67 66 65 64 63 i pull-down cmos a[6:0]: address bus in erpom, intel and motorola modes, these pins are the address bus of the microprocessor interface. sdi: serial data input in serial mode, this pin is used as the serial data input. address and data on this pin are seri- ally clocked into the device on the rising edge of sclk. clke: sclk active edge selection in serial mode, this pin selects the active edge of sclk to update the sdo: high - the falling edge; low - the rising edge. in multiplexed mode, a0/sdi, a1/clke and a[6:2] pins should be connected to ground. in serial mode, a[6:2] pins should be connected to ground. ad0 / sdo ad1 ad2 ad3 ad4 ad5 ad6 ad7 83 82 81 80 79 78 77 76 i/o pull-down cmos ad[7:0]: address / data bus in eprom, intel and motorola modes, these pins are the bi-directional data bus of the micro- processor interface. in multiplexed mode, these pins are the bi-directional address/data bus of the microproces- sor interface. sdo: serial data output in serial mode, this pin is used as the serial data output. data on this pin is serially clocked out of the device on the active edge of sclk. in serial mode, ad[7:1] pins should be connected to ground. wr 71 i pull-up cmos wr : write operation in multiplexed and intel modes, this pin is asserted low to initiate a write operation. in motorola mode, this pin is asserted low to initiate a write operation or s asserted high to ini- tiate a read operation. in eprom and serial modes, this pin should be connected to ground. rd 72 i pull-up cmos rd : read operation in multiplexed and intel modes, this pin is asserted low to initiate a read operation. in eprom, motorola and serial modes, this pin should be connected to ground. table 1: pin description (continued) name pin no. i/o type description 1
IDT82V3285 wan pl l pin description 16 december 9, 2008 ale / sclk 73 i pull-down cmos ale: address latch enable in multiplexed mode, the address on ad[7:0] pins is sampled into the device on the falling edge of ale. sclk: shift clock in serial mode, a shift clock is input on this pin. data on sdi is sampled by the device on the rising edge of sclk. data on sdo is updated on the active edge of sclk. the active edge is determined by the clke. in eprom, intel and motorola modes, this pin should be connected to ground. rdy 75 o cmos rdy: ready/data acknowledge in multiplexed and intel modes, a high level on this pin indicates that a read/write cycle is completed. a low level on this pin indicates that wait state must be inserted. in motorola mode, a low level on this pin indicates that valid information on the data bus is ready for a read operation or acknowledges the acceptance of the written data during a write operation. in eprom and serial modes, this pin should be connected to ground. jtag (per ieee 1149.1) trst 2 i pull-down cmos trst : jtag test reset (active low) a low signal on this pin resets the jtag test port. this pin should be connected to ground when jtag is not used. tms 7 i pull-up cmos tms: jtag test mode select the signal on this pin controls the jtag test performance and is sampled on the rising edge of tck. tck 9 i pull-down cmos tck: jtag test clock the clock for the jtag test is input on this pin. tdi and tms are sampled on the rising edge of tck and tdo is updated on the falling edge of tck. if tck is idle at a low level, all stored-state devices contained in the test logic will indefinitely retain their state. tdi 23 i pull-up cmos tdi: jtag test data input the test data is input on this pin. it is clocked into the device on the rising edge of tck. tdo 21 o cmos tdo: jtag test data output the test data is output on this pin. it is clocked out of the device on the falling edge of tck. tdo pin outputs a high impedance signal except during the process of data scanning. this pin can indicate the interrupt of t0 selected input clock fail, as determined by the los_flag_on_tdo bit (b6, 0bh). refer to chapter 3.8.1 input clock validity for details. power & ground vddd1 vddd2 vddd3 vddd4 vddd5 vddd6 vddd7 12 16 13 50 61 85 86 power - vdddn: 3.3 v digital power supply vdddn connections should be connected using the recommended decoupling scheme shown in figure 14 . table 1: pin description (continued) name pin no. i/o type description 1
IDT82V3285 wan pl l pin description 17 december 9, 2008 vdda1 vdda2 vdda3 6 19 91 power - vddan: 3.3 v analog power supply vddan connections should be connected using the recommended decoupling scheme shown in figure 14 . vddd8 26 power - vddd8: 3.3 v digital power supply vdd_diff1 33 power - vdd_diff1: 3.3 v power supply for out4 vdd_diff2 39 power - vdd_diff2: 3.3 v power supply for out5 dgnd1 dgnd2 dgnd3 dgnd4 dgnd5 dgnd6 dgnd7 11 15 14 49 62 84 87 ground - dgndn: digital ground agnd1 agnd2 agnd3 5 20 92 ground - agndn: analog ground gnd_diff1 32 ground - gnd_diff: ground for out4 gnd_diff2 38 ground - gnd_diff: ground for out5 dgnd8 29 ground - dgnd8: digital ground agnd 1 ground - agnd: analog ground others ic1 ic2 ic3 ic4 ic5 ic6 ic7 3 4 17 22 96 97 98 -- ic: internally connected internal use. these pins should be left open for normal operation. nc 24, 25, 27, 28, 44, 48, 51, 52, 53, 55, 56, 57, 88, 89, 95 -- nc: not connected note: 1. all the unused input pins should be connected to ground ; the output of all the unused output pins are don?t-care. 2. the contents in the brackets indicate the position of the register bit/bits. 3. n x 8 khz: 1 < n < 19440. 4. n x e1: n = 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64. 5. n x t1: n = 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96. 6. n x 13.0 mhz: n = 1, 2, 4. 7. n x 3.84 mhz: n = 1, 2, 4, 8, 16, 10, 20, 40. table 1: pin description (continued) name pin no. i/o type description 1
IDT82V3285 wan pl l functional description 18 december 9, 2008 3 functional description 3.1 reset the reset operation resets all regi sters and state machines to their default value or status. after power on, the device must be reset for normal operation. for a complete reset, the rst pin must be asserted low for at least 50 s. after the rst pin is pulled high, the device will still be in reset state for 500 ms (typical). if the rst pin is held low continuously, the device remains in reset state. 3.2 master clock a nominal 12.8000 mhz clock, provi ded by a crystal oscillator, is input on the osci pin. this clock is provided for the device as a master clock. the master clock is used as a reference clock for all the internal circuits. a better active edge of the master clock is selected by the osc_edge bit to improve jitter and wander performance. in fact, an offset from the nominal frequency may input on the osci pin. this offset can be compensated by setting the nominal_freq_value[23:0] bits. the calibration range is within 741 ppm. the performance of the master clock should meet gr-1244-core, gr-253-core, itu-t g.812 and g.813 criteria. table 2: related bit / register in chapter 3.2 bit register address (hex) nominal_freq_value[23:0] nominal_freq [23:16]_cnfg, nominal_freq[15:8]_cnfg, nominal_freq[7:0]_cnfg 06, 05, 04 osc_edge differential_in_out_osci_cnfg 0a
IDT82V3285 wan pl l functional description 19 december 9, 2008 3.3 input clocks & frame sync signal altogether 5 clocks and 1 frame sync signal are input to the device. 3.3.1 input clocks the device provides 5 input clock ports. according to the input port technol ogy, the input ports support the fol- lowing technologies: ? pecl/lvds ? cmos according to the input clock source , the following clock sources are supported: ? t1: recovered clock from stm-n or oc-n ? t2: pdh network synchronization timing ? t3: external synchroniz ation reference timing in1, in2 and in5 support cmos input signal only and the clock sources can be from t1, t2 or t3. in3 and in4 support pecl/lvds input signal only and automatically detect whether the signal is pecl or lvds. the clock sources can be from t1, t2 or t3. for sdh and sonet networks, the default frequency is different. sonet / sdh frequency selection is controlled by the in_sonet_sdh bit. during reset, the default value of the in_sonet_sdh bit is deter- mined by the sonet/ sdh pin: high for sonet and low for sdh. after reset, the input signal on the sonet/ sdh pin takes no effect. 3.3.2 frame sync input signals a 2 khz, 4 khz or 8 khz frame sync signal is input on the ex_sync1 pin. it is a cmos input. the input frequency should match the setting in the sync_freq[1:0] bits. the frame sync input signal is us ed for frame sync output signal syn- chronization. refer to chapter 3.13.2 frame sync output signals for details. table 3: related bit / register in chapter 3.3 bit register address (hex) in_sonet_sdh input_mode_cnfg 09 sync_freq[1:0]
IDT82V3285 wan pl l functional description 20 december 9, 2008 3.4 input clock pre-divider each input clock is assigned an inte rnal pre-divider. the pre-divider is used to divide the clock frequency down to the dpll required fre- quency, which is no more than 38.88 mhz. for in1 ~ in5, the dpll required frequency is set by the correspond- ing in_freq[3:0] bits. if the input clock is of 2 khz, 4 khz or 8 khz, the pre-divider is bypassed automatically and the co rresponding in_freq[3:0] bits should be set to match the input frequency; the input clock can be inverted, as determined by the in_2k_4k_8k_inv bit. each pre-divider consists of a hf (high frequency) divider (only available for in3 and in4), a divn divider and a lock 8k divider, as shown in figure 3 . the hf divider, which is only av ailable for in3 and in4, should be used when the input clock is higher than ( > ) 155.52 mhz. the input clock can be divided by 4, 5 or c an bypass the hf divider, as deter- mined by the in3_div[1:0]/in4_div[1:0] bits correspondingly. either the divn divider or the lo ck 8k divider can be used or both can be bypassed, as determined by the direct_div bit and the lock_8k bit. when the divn divider is used for inn (1 n 5), the division factor setting should observe the following order: 1. select an input clock by the pre_div_ch_value[3:0] bits; 2. write the lower eight bits of the division factor to the pre_divn_value[7:0] bits; 3. write the higher eight bits of the division factor to the pre_divn_value[14:8] bits. once the division factor is set for the input clock selected by the pre_div_ch_value[3:0] bits, it is valid until a different division factor is set for the same input clock. the division factor is calculated as fol- lows: division factor = (the frequency of the clock input to the divn divider the frequency of the dpll required clock set by the in_freq[3:0] bits) - 1 the divn divider can only divide the input clock whose frequency is lower than ( < ) 155.52 mhz. when the lock 8k divider is used, the input clock is divided down to 8 khz automatically. the pre-divider configuration and the division factor setting depend on the input clock on one of the in1 ~ in5 pins and the dpll required clock. here is an example: the input clock on the in4 pin is 622.08 mhz; the dpll required clock is 6.48 mhz by programming the in _freq[3:0] bits of register in4 to ?0010?. do the following step by step to divide the input clock: 1. use the hf divider to divi de the clock down to 155.52 mhz: 622.08 155.52 = 4, so set the in4_div[1:0] bits to ?01?; 2. use the divn divider to di vide the clock down to 6.48 mhz: set the pre_div_ch_value[3:0] bits to ?0110?; set the direct_div bit in register in4_cnfg to ?1? and the lock_8k bit in register in4_cnfg to ?0?; 155.52 6.48 = 24; 24 - 1 = 23, so set the pre_divn_value[14:0] bits to ?10111?. figure 3. pre-divider for an input clock table 4: related bit / register in chapter 3.4 bit register address (hex) in3_div[1:0] in3_in4_hf_div_cnfg 18 in4_div[1:0] in_freq[3:0] in1_cnfg ~ in5_cnfg 16 ~ 17, 19 ~ 1a, 1f in_2k_4k_8k_inv fr_mfr_sync_cnfg 74 direct_div in1_cnfg ~ in5_cnfg 16 ~ 17, 19 ~ 1a, 1f lock_8k pre_div_ch_value[3:0] pre_div_ch_cnfg 23 pre_divn_value[14:0] pr e_divn[14:8]_cnfg, pre_divn[7:0]_cnfg 25, 24 input clock inn (1 n 5) divn divider lock 8k divider hf divider (for in3 & in4 only) pre-divider in3_div[1:0] bits / in4_div[1:0] bits direct_div bit lock_8k bit dpll required clock
IDT82V3285 wan pl l functional description 21 december 9, 2008 3.5 input clock quality monitoring the qualities of all the input cloc ks are always monitored in the fol- lowing aspects: ? activity ? frequency activity and frequency monitoring are conducted on all the input clocks. the qualified clocks are availabl e for t0/t4 dpll selection. the t0 and t4 selected input clocks have to be monitored further. refer to chapter 3.7 selected input clock monitoring for details. 3.5.1 activity monitoring activity is monitored by using an internal leaky bucket accumulator, as shown in figure 4 . each input clock is assigned an in ternal leaky bucket accumulator. the input clock is monitored for each period of 128 ms and the internal leaky bucket accumulator increases by 1 when an event is detected; it decreases by 1 if no event is detect ed within the period set by the decay rate. the event is that an input cl ock drifts outside (>) 500 ppm with respect to the master clock within a 128 ms period. there are four configurations (0 - 3) for a leaky bucket accumulator. the leaky bucket configuration for an input clock is selected by the cor- responding bucket_sel[1:0] bits. ea ch leaky bucket configuration consists of four elements: upper thre shold, lower threshold, bucket size and decay rate. the bucket size is the capability of the accumulator. if the number of the accumulated events reaches the bucket size, the accumulator will stop increasing even if further event s are detected. the upper threshold is a point above which a no-activity al arm is raised. the lower threshold is a point below which the no-activity alarm is cleared. the decay rate is a certain period during which the accumulator decreases by 1 if no event is detected. the leaky bucket configuration is programmed by one of four groups of register bits: the bucket_size_n_data[7:0] bits, the upper_ threshold_n_data[7:0] bits, the lower_threshold_n_ data[7:0] bits and the decay_rate_n_data[1:0] bits respectively; ?n? is 3. the no-activity alarm status of t he input clock is indicated by the inn_no_activity_alarm bit (1 n 5). the input clock with a no- activity alarm is disqualified for clock selec- tion for t0/t4 dpll. figure 4. input clock activity monitoring input clock leaky bucket accumulator no-activity alarm indication decay rate bucket size upper threshold lower threshold 0 clock signal with no event clock signal with events
IDT82V3285 wan pl l functional description 22 december 9, 2008 3.5.2 frequency monitoring frequency is monitored by compari ng the input clock with a refer- ence clock. the reference clock can be derived from the master clock or the output of t0 dpll, as determined by the freq_mon_clk bit. a frequency hard alarm threshold is set for frequency monitoring. if the freq_mon_hard_en bit is ?1?, a frequency hard alarm is raised when the frequency of the input clock wi th respect to the reference clock is above the threshold; the alarm is cleared when the frequency is below the threshold. the frequency hard alarm threshold can be calculated as follows: frequency hard alarm thres hold (ppm) = (all_freq_hard_ threshold[3:0] + 1) x freq_mon_factor[3:0] if the freq_mon_hard_en bit is ?1?, the frequency hard alarm status of the input clock is indicated by the inn_freq_hard_alarm bit (1 n 5). when the freq_mon_hard_ en bit is ?0?, no frequency hard alarm is raised even if the i nput clock is above the frequency hard alarm threshold. the input clock with a frequency hard alarm is disqualified for clock selection for t0/t4 dpll. in addition, if the input clock is 2 khz, 4 khz or 8 khz, its clock edges with respect to the reference clock are monitored. if any edge drifts out- side 5%, the input clock is disqual ified for clock selection for t0/t4 dpll. the input clock is qualified if any edge drifts inside 5%. this function is supported only when the in_noise_window bit is ?1?. the frequency of each input clock with respect to the reference clock can be read by doing the following step by step: 1. select an input clock by setting the in_freq_read_ch[3:0] bits; 2. read the value in the in_freq_value[7:0] bits and calculate as follows: input clock frequency (ppm) = in_freq_value[7:0] x freq_mon_factor[3:0] note that the value set by the freq_mon_factor[3:0] bits depends on the application. table 5: related bit / register in chapter 3.5 bit register address (hex) bucket_size_n_data[7:0] (n = 3) bucket_size_3_cnfg 3f upper_threshold_n_data[7:0] (n = 3) upper_threshold_3_cnfg 3d lower_threshold_n_data[7:0] (n = 3) lower_threshold_3_cnfg 3e decay_rate_n_data[1:0] (n = 3) decay_rate_3_cnfg 40 bucket_sel[1:0] in1_cnfg ~ in5_cnfg 16 ~ 17, 19 ~ 1a, 1f inn_no_activity_alarm ( 1 n 5 ) in1_in2_sts, in3_in4_sts, in5_sts 44~ 45, 48 inn_freq_hard_alarm ( 1 n 5 ) freq_mon_clk mon_sw_pbo_cnfg 0b freq_mon_hard_en all_freq_hard_thresh old[3:0] all_freq_mon_threshold_cnfg 2f freq_mon_factor[3:0] freq_mon_factor_cnfg 2e in_noise_window ph ase_mon_pbo_cnfg 78 in_freq_read_ch[3:0] in_freq_read_ch_cnfg 41 in_freq_value[7:0] in_freq_read_sts 42
IDT82V3285 wan pl l functional description 23 december 9, 2008 3.6 t0 / t4 dpll input clock selection an input clock is selected for t0 dpll and for t4 dpll respectively. for t0 path, the ext_sw bit and the t0_input_sel[3:0] bits deter- mine the input clock selection, as shown in table 6 : for t4 path, the t4 dpll may lock to a t0 dpll output or lock inde- pendently from t0 path, as deter mined by the t4_lock_t0 bit. when the t4 dpll locks to the t0 dpll output, the t4 selected input clock is a 77.76 mhz or 8 khz signal from the t0 dpll 77.76 mhz path (refer to chapter 3.11.5.1 t0 path ), as determined by the t0_for_t4 bit. when the t4 path locks independently from the t0 path, the t4 dpll input clock selection is determined by the t4_input_sel[3:0] bits. refer to table 7 : external fast selection is do ne between in1/in3 and in2/in4 pairs. forced selection is done by setting the related registers. automatic selection is done based on the results of input clocks qual- ity monitoring and the relat ed registers configuration. the selected input clock is attempted to be locked in t0/t4 dpll. 3.6.1 external fast selection (t0 only) the external fast selection is supported by t0 path only. in external fast selection, only in1/in3 and in2 /in4 pairs are available for selec- tion. refer to figure 5 . the results of input clocks quality monitoring (refer to chapter 3.5 input clock quality monitoring ) do not affect input clock selection. the t0 input clock selection is determined by the ff_srcsw pin after reset (this pin determines the default value of the ext_sw bit dur- ing reset, refer to chapter 2 pin description ), the in1_sel_priority[3:0] bits and the in2_sel_priority[3:0] bits, as shown in figure 5 and table 8 : figure 5. external fast selection table 6: input clock selection for t0 path control bits input clock selection ext_sw t0_input_sel[3:0] 1 don?t-care external fast selection 0 other than 0000 forced selection 0000 automatic selection table 7: input clock selection for t4 path control bits - t4_input_sel[3:0] input clock selection other than 0000 forced selection 0000 automatic selection ff_srcsw pin in1 in3 in2 in4 in1_sel_priority[3:0] bits in2_sel_priority[3:0] bits attempted to be locked in t0 dpll table 8: external fast selection control pin & bits selected input clock ff_srcsw (after reset) in1_sel_pri ority[3:0] in2_sel_priority[3:0] high 0000 don?t-care in3 other than 0000 in1 low don?t-care 0000 in4 other than 0000 in2
IDT82V3285 wan pl l functional description 24 december 9, 2008 3.6.2 forced selection in forced selection, the selected input clock is set by the t0_input_sel[3:0] / t4_input_sel[3:0] bits. the results of input clocks quality monitoring (refer to chapter 3.5 input clock quality moni- toring ) do not affect the input clock selection. 3.6.3 automatic selection in automatic selection, the input clock selection is determined by its validity, priority and locking allo wance configuration. the validity depends on the results of input cl ock quality monitoring (refer to chapter 3.5 input clock quality monitoring ). locking allowance is con- figured by the corresponding inn_valid bit(1 n 5). refer to figure 6 . in all the qualified input clocks, the one with the highest priority is selected. the priority is set by the corresponding inn_sel_priority[3:0] bits (1 n 5). if more than one qualified input clock inn is available and has the same priority, the input clock with the smallest ?n? is selected. figure 6. qualified input clocks for automatic selection table 9: related bit / register in chapter 3.6 bit register address (hex) ext_sw mon_sw_pbo_cnfg 0b t0_input_sel[3:0] t0_input_sel_cnfg 50 t4_lock_t0 t4_input_sel_cnfg 51 t0_for_t4 t4_input_sel[3:0] inn_sel_priority[3:0] ( 1 n 5 ) in1_in2_sel_priority_cnfg in3_in4_sel_priority_cnfg in5_sel_priority_cnfg 27 ~ 28, 2b inn_valid ( 1 n 5 ) remote_input_valid1_cnfg, remote_input_valid2_cnfg 4c, 4d inn ( 1 n 5 ) input_valid1_sts, input_valid2_sts 4a, 4b t4_t0_sel t4_t0_reg_sel_cnfg 07 note: * the setting in the 26 ~ 2c registers is either for t0 pa th or for t4 path, as determined by the t4_t0_sel bit. validity priority inn_sel_priority[3:0] '0000', ((1 n 5)) locking allowance inn_valid = '0', ((1 n 5)) yes no no no yes yes all qualified input clocks are avai lable for automatic selection input clock quality monitoring (activity, frequency) inn = '1', (1 n 5)
IDT82V3285 wan pl l functional description 25 december 9, 2008 3.7 selected input clock monitoring the quality of the selected input cl ock is always monitored (refer to chapter 3.5 input clock quality monitoring ) and the dpll locking status is always monitored. 3.7.1 t0 / t4 dpll locking detection the following events are always monitored: ? fast loss; ? coarse phase loss; ? fine phase loss; ? hard limit exceeding. 3.7.1.1 fast loss a fast loss is triggered when the selected input clock misses 2 con- secutive clock cycles. it is cleared once an active clock edge is detected. for t0 path, the occurrence of the fast loss will result in t0 dpll being unlocked if the fast_los_sw bit is ?1?. for t4 path, the occur- rence of the fast loss will result in t4 dpll being unlocked regardless of the fast_los_sw bit. 3.7.1.2 coarse phase loss the t0/t4 dpll compares the selected input clock with the feed- back signal. if the phase-compared re sult exceeds the coarse phase limit, a coarse phase loss is trigger ed. it is cleared once the phase-com- pared result is within the coarse phase limit. when the selected input clock is of 2 khz, 4 khz or 8 khz, the coarse phase limit depends on the multi_ph_8k_4k_2k_en bit, the wide_en bit and the ph_los_coarse_limt[3:0] bits. refer to table 10 . when the selected input clock is of other frequencies than 2 khz, 4 khz and 8 khz, the coarse phase limit depends on the wide_en bit and the ph_los_coarse_limt[3:0] bits. refer to table 11 . the occurrence of the coarse phase loss will result in t0/t4 dpll being unlocked if the coarse_p h_los_limt_en bit is ?1?. 3.7.1.3 fine phase loss the t0/t4 dpll compares the selected input clock with the feed- back signal. if the phase-compared re sult exceeds the fine phase limit programmed by the ph_los_fine_limt[2:0] bits, a fine phase loss is triggered. it is cleared once the phase-co mpared result is within the fine phase limit. the occurrence of the fine phase loss will result in t0/t4 dpll being unlocked if the fine_ph_los_limt_en bit is ?1?. 3.7.1.4 hard limit exceeding two limits are available for this monitoring. they are dpll soft limit and dpll hard limit. when the frequency of the dpll output with respect to the master clock exceeds the dpll soft / hard limit, a dpll soft / hard alarm will be raised; the alarm is cleared once the frequency is within the corresponding limit. t he occurrence of the dpll soft alarm does not affect the t0/t4 dpll locking status. the dpll soft alarm is indicated by the corresponding t0_dpll_soft_freq_alarm / t4_dpll_soft_freq_alarm bit. the occurrence of the dpll hard alarm will result in t0/t4 dpll being unlocked if the freq_limt_ph_los bit is ?1?. the dpll soft limit is set by the dpll_freq_soft_limt[6:0] bits and can be calculated as follows: dpll soft limit (ppm) = dpll_freq_soft_limt[6:0] x 0.724 the dpll hard limit is set by the dpll_freq_hard_limt[15:0] bits and can be calculated as follows: dpll hard limit (ppm) = dpll_fr eq_hard_limt[15:0] x 0.0014 3.7.2 locking status the dpll locking status depends on the locking monitoring results. the dpll is in locked state if none of the following events is triggered during 2 seconds; otherwise, the dpll is unlocked. ? fast loss (the fast_los_sw bit is ?1?); ? coarse phase loss (the coarse_ph_los_limt_en bit is ?1?); ? fine phase loss (the fine_ph_los_limt_en bit is ?1?); ? dpll hard alarm (the freq_limt_ph_los bit is ?1?). if the fast_los_sw bit, the coarse_ph_los_limt_en bit, the fine_ph_los_limt_en bit or the fr eq_limt_ph_los bit is ?0?, the dpll locking status will not be affected even if the corresponding event is triggered. if all these bits are ?0?, the dpll will be in locked state in 2 seconds. the dpll locking status is i ndicated by the t0_dpll_lock / t4_dpll_lock bit. the t4_sts 1 bit will be set when the locking status of the t4 dpll changes (from ?locked? to ?unlocked? or from ?unlocked? to ?locked?). if the t4_sts 2 bit is ?1?, an interrupt will be generated. table 10: coarse phase limit pr ogramming (the selected input clock of 2 khz, 4 khz or 8 khz) multi_ph_8k_4k _2k_en wide_en coarse phase limit 0 don?t-care 1 ui 1 01 ui 1 set by the ph_los_coarse_limt[3:0] bits table 11: coarse phase limit programming (the selected input clock of other than 2 khz, 4 khz and 8 khz) wide_en coarse phase limit 01 ui 1 set by the ph_los_coarse_limt[3:0] bits
IDT82V3285 wan pl l functional description 26 december 9, 2008 3.7.3 phase lock alarm (t0 only) a phase lock alarm will be raised when the selected input clock can not be locked in t0 dpll within a certain period. this period can be cal- culated as follows: period (sec.) = time_out_val ue[5:0] x multi_factor[1:0] the phase lock alarm is indicated by the corresponding inn_ph_lock_alarm bit (1 n 5). the phase lock alarm can be cleared by the following two ways, as selected by the ph_alarm_timeout bit: ? be cleared when a ?1? is written to the corresponding inn_ph_lock_alarm bit; ? be cleared after the period ( = time_out_value[5:0] x multi_factor[1:0] in seconds ) which starts from when the alarm is raised. the selected input clock with a phase lock alarm is disqualified for t0 dpll locking. note that no phase lock alarm is ra ised if the t4 selected input clock can not be locked. table 12: related bit / register in chapter 3.7 bit register address (hex) fast_los_sw phase_loss_fine_limit_cnfg 5b * ph_los_fine_limt[2:0] fine_ph_los_limt_en multi_ph_8k_4k_2k_en phase_loss_coarse_limit_cnfg 5a * wide_en ph_los_coarse_limt[3:0] coarse_ph_los_limt_en t0_dpll_soft_freq_alarm operating_sts 52 t4_dpll_soft_freq_alarm t0_dpll_lock t4_dpll_lock dpll_freq_soft_limt[6:0] dpll_freq_soft_limit_cnfg 65 freq_limt_ph_los dpll_freq_hard_limt[15:0] dpll_freq_hard_limit[15:8]_cnfg, dpll_freq_hard_limit[7:0]_cnfg 67, 66 t4_sts 1 interrupts3_sts 0f t4_sts 2 interrupts3_enable_cnfg 12 time_out_value[5:0] phase_alarm_time _out_cnfg 08 multi_factor[1:0] inn_ph_loc k_alarm ( 1 n 5 ) in1_in2_sts, in3_in4_sts, in5_sts 44 ~ 45, 48 ph_alarm_timeout input_mode_cnfg 09 t4_t0_sel t4_t0_reg_sel_cnfg 07 note: * the setting in the 5a and 5b registers is either for t0 path or for t4 path, as determined by the t4_t0_sel bit.
IDT82V3285 wan pl l functional description 27 december 9, 2008 3.8 selected input clock switch if the input clock is selected by exte rnal fast selection or by forced selection, it can be switched by se tting the related registers (refer to chapter 3.6.1 external fast selection (t0 only) & chapter 3.6.2 forced selection ) any time. in this case, whether the input clock is qualified for dpll locking does not affect the clock switch. if the t4 selected input clock is a t0 dpll output, it can only be switched by setting the t0_for_t4 bit. when the input clock is selected by automatic selection, the input clock switch depends on its validity, priority and locking allowance con- figuration. if the current selected input clock is disqualified, a new quali- fied input clock may be switched to. 3.8.1 input clock validity for all the input clocks, the validity depends on the results of input clock quality monitoring (refer to chapter 3.5 input clock quality moni- toring ). when all of the following condition s are satisfied, the input clock is valid; otherwise, it is invalid. ? no no-activity alarm (the inn_no_activity_alarm bit is ?0?); ? no frequency hard alarm (the inn_freq_hard_alarm bit is ?0?); ? if the in_noise_window bit is ?1?, all the edges of the input clock of 2 khz, 4 khz or 8 khz drift inside 5%; if the in_noise_window bit is ?0?, this condition is ignored. the validity qualification of the t0 selected input clock is different from that of the t4 selected input clo ck. the validity qualification of the t4 selected input clock is the same as the above. the t0 selected input clock is valid when all of the above and the following conditions are sat- isfied; otherwise, it is invalid. ? no phase lock alarm, i.e., the inn_ph_lock_alarm bit is ?0?; ? if the ultr_fast_sw bit is ?1?, the t0 selected input clock misses less than (<) 2 consecutive clock cycles; if the ultr_fast_sw bit is ?0?, this condition is ignored. the validities of all the input clocks are indicated by the inn 1 bit (1 n 5). when the input clock validity c hanges (from ?valid? to ?invalid? or from ?invalid? to ?valid?), the inn 2 bit will be set. if the inn 3 bit is ?1?, an interrupt will be generated. when the t0 selected input clock has failed, i.e., the validity of the t0 selected input clock changes from ?valid? to ?invalid?, the t0_main_ref_failed 1 bit will be set. if the t0_main_ref_failed 2 bit is ?1?, an interrupt will be generat ed. this interrupt can also be indi- cated by hardware - the tdo pin, as determined by the los_flag_to_tdo bit. when the tdo pin is used to indicate this interrupt, it will be set high when this interrupt is generated and will remain high until this interrupt is cleared. 3.8.2 selected input clock switch when the device is configured as automatic input clock selection, t0 input clock switch is different from t4 input clock switch. for t0 path, revertive and non-revertive switches are supported, as selected by the revertive_mode bit. for t4 path, only revertive switch is supported. the difference between revertive and non-revertive switches is that whether the selected input cl ock is switched when another qualified input clock with a higher priority t han the current selected input clock is available for selection. in non-reve rtive switch, input clock switch is minimized. conditions of the qualified input cloc ks available for t0 selection are different from that for t4 selection, as shown in table 13 : the input clock is disqualified if any of the above conditions is not satisfied. in summary, the selected input clock can be switched by: ? external fast selection (supported by t0 path only); ? forced selection; ? revertive switch; ? non-revertive switch (supported by t0 path only); ? t4 dpll locked to t0 dpll output (supported by t4 path only). 3.8.2.1 revertive switch in revertive switch, the selected input clock is switched when another qualified input clock with a higher priority than the current selected input clock is available. the selected input clock is switched if any of the following is satis- fied: ? the selected input clock is disqualified; ? another qualified input clock with a higher priority than the selected input clock is available. a qualified input clock with the highest priority is selected by revertive switch. if more than one qualified input clock inn is available and has the same priority, the input clock with the smallest ?n? is selected. table 13: conditions of qualified input clocks available for t0 & t4 selection conditions of qualified input clocks available for t0 & t4 selection t0 ? valid, i.e., the inn 1 bit is ?1?; ? priority enabled, i.e., the corresponding inn_sel_priority[3:0] bits are not ?0000?; ? locking to the input clock is allowed, i.e., the corresponding inn_valid bit is ?0?. t4 ? valid (all the validity conditions listed in chapter 3.8.1 input clock valid- ity are satisfied); ? priority enabled, i.e., the corresponding inn_sel_priority[3:0] bits are not ?0000?; ? locking to the input clock is allowed, i.e., the corresponding inn_valid bit is ?0?.
IDT82V3285 wan pl l functional description 28 december 9, 2008 3.8.2.2 non-revertive switch (t0 only) in non-revertive switch, the t0 selected input clock is not switched when another qualified input clock with a higher priority than the current selected input clock is available. in this case, the selected input clock is switched and a qualified input clock with the highest priority is selected only when the t0 selected input clock is disqualified. if more than one qualified input clock is available and has the same priority, the input clock with the smallest ?n? is selected. 3.8.3 selected / qualified input clocks indication the selected input clock is indicated by the currently_selected_input[3:0] bits. note if the t4 selected input clock is a t0 dpll output, it can not be indicated by these bits. the qualified input clocks with the three highest priorities are indi- cated by highest_priority_validated[3:0] bits, the second_ priority_validated[3:0] bits and the third_priority _validated[3:0] bits respectively. if more than one input clock inn has the same priority, the input clock with the smallest ?n? is indicated by the highest_priority_validated[3:0] bits. when the device is configured in automatic selection and revertive switch is enabled, the input clock indicated by the currently_selected_input[3:0] bits is the same as the one indi- cated by the highest_priority_validated[3:0] bits; otherwise, they are not the same. when all the input clocks for t4 path become unqualified, the input_to_t4 1 bit will be set. if the input_to_t4 2 bit is ?1?, an inter- rupt will be generated. table 14: related bit / register in chapter 3.8 bit register address (hex) t0_for_t4 t4_input_sel_cnfg 51 inn 1 ( 1 n 5 ) input_valid1_sts, input_valid2_sts 4a, 4b inn 2 ( 1 n 5 ) interrupts1_sts, interrupts2_sts 0d, 0e inn 3 ( 1 n 5 ) interrupts1_enable_cnfg, interrupts2_enable_cnfg 10, 11 inn_no_activity_alarm (1 n 5) in1_in2_sts, in3_in4_sts, in5_sts 44 ~ 45, 48 inn_freq_hard_alarm (1 n 5) inn_ph_lock_alarm ( 1 n 5 ) in_noise_window phase_mon_pbo_cnfg 78 ultr_fast_sw mon_sw_pbo_cnfg 0b los_flag_to_tdo t0_main_ref_failed 1 interrupts2_sts 0e t0_main_ref_failed 2 interrupts2_enable_cnfg 11 input_to_t4 1 interrupts3_sts 0f input_to_t4 2 interrupts3_e nable_cnfg 12 revertive_mode input_mode_cnfg 09 inn_sel_priority[3:0] ( 1 n 5 ) in1_in2_sel_priority_cnfg, in3_in4_sel_priority_cnfg, in5_sel_priority_cnfg 27 ~ 28, 2b inn_valid ( 1 n 5 ) remote_input_valid1_cnfg, remote_input_valid2_cnfg 4c, 4d currently_selected_input[3:0] priority_table1_sts 4e * highest_priority_validated[3:0] second_priority_validated[3:0] priority_table2_sts 4f * third_priority_validated[3:0] t4_t0_sel t4_t0_reg_sel_cnfg 07 note: * the setting in the 26 ~ 2c, 4e and 4f registers is either fo r t0 path or for t4 path, as determined by the t4_t0_sel bit.
IDT82V3285 wan pl l functional description 29 december 9, 2008 3.9 selected input clock status vs. dpll operating mode the operating modes supported by t0 dpll are more complex than the ones supported by t4 dpll for t0 path is the main one. t0 dpll supports three primary operating modes: free-run, locked and hold- over, and three secondary, tempor ary operating modes: pre-locked, pre-locked2 and lost-phase. t4 dpll supports three operating modes: free-run, locked and hol dover. the operating modes of t0 dpll and t4 dpll can be switched automatically or by force, as con- trolled by the t0_operatin g_mode[2:0] / t4_operating_ mode[2:0] bits respectively. when the operating mode is switched by force, the operating mode switch is under external control and t he status of the selected input clock takes no effect to the operating mode selection. the forced operating mode switch is applicable for special cases, such as testing. when the operating mode is switched automatically, the internal state machines for t0 and for t4 automatically determine the operating mode respectively. 3.9.1 t0 selected input clock vs. dpll operating mode the t0 dpll operating mode is controlled by the t0_operating_mode[2:0] bits, as shown in table 15 : when the operating mode is switched automatically, the operation of the internal state machine is shown in figure 7 . whether the operating mode is under ex ternal control or is switched automatically, the current operating mode is always indicated by the t0_dpll_operating_mode[2:0] bits. when the operating mode switches, the t0_operating_mode 1 bit will be set. if the t0_operating_mode 2 bit is ?1?, an interrupt will be generated. table 15: t0 dpll op erating mode control t0_operating_mode[2:0] t 0 dpll operating mode 000 automatic 001 forced - free-run 010 forced - holdover 100 forced - locked 101 forced - pre-locked2 110 forced - pre-locked 111 forced - lost-phase
IDT82V3285 wan pl l functional description 30 december 9, 2008 figure 7. t0 selected input cloc k vs. dpll automatic operating mode notes to figure 7 : 1. reset. 2. an input clock is selected. 3. the t0 selected input clock is disqualified and no qualified input clock is available. 4. the t0 selected input clock is switched to another one. 5. the t0 selected input clock is locked (the t0_dpll_lock bit is ?1?). 6. the t0 selected input clock is disqualified and no qualified input clock is available. 7. the t0 selected input clock is unl ocked (the t0_dpll_lock bit is ?0?). 8. the t0 selected input clock is lock ed again (the t0_dpll_lock bit is ?1?). 9. the t0 selected input clock is switched to another one. 10. the t0 selected input clock is locked (the t0_dpll_lock bit is ?1?). 11. the t0 selected input clock is disqualified and no qualified input clock is available. 12. the t0 selected input clock is switched to another one. 13. the t0 selected input clock is disqualified and no qualified input clock is available. 14. an input clock is selected. 15. the t0 selected input clock is switched to another one. free-run mode 1 pre-locked mode 2 3 4 locked mode 5 lost-phase mode holdover mode 7 8 pre-locked2 mode 13 14 15 6 12 11 9 10
IDT82V3285 wan pl l functional description 31 december 9, 2008 the causes of item 4, 9, 12, 15 - ?the t0 selected input clock is switched to another one? - are: (the t0 selected input clock is disquali- fied and another input clock is switched to) or (in revertive switch, a qualified input clock with a hi gher priority is switched to) or (the t0 selected input clock is switched to another one by external fast selec- tion or forced selection). refer to table 13 for details about the input clock qualification for t0 path. 3.9.2 t4 selected input clock vs. dpll operating mode the t4 dpll operating mode is controlled by the t4_operating_mode[2:0] bits, as shown in table 16 : when the operating mode is switched automatically, the operation of the internal state machine is shown in figure 8 : figure 8. t4 selected inpu t clock vs. dpll automatic operating mode notes to figure 8 : 1. reset. 2. an input clock is selected. 3. (the t4 selected input clock is disqualified) or (a qualified input clock with a higher priority is switched to) or (the t4 selected input clock is switched to another one by forced selection) or (when t4 dpll locks to the t0 dpll output, the t4 selected input clock is switched by setting the t0_for_t4 bit). 4. an input clock is selected. 5. no input clock is selected. refer to table 13 for details about the input clock qualification for t4 path. table 16: t4 dpll operating mode control t4_operating_mode[2:0] t4 dpll operating mode 000 automatic 001 forced - free-run 010 forced - holdover 100 forced - locked 2 locked mode holdover mode free-run mode 1 3 4 5 table 17: related bit / register in chapter 3.9 bit register address (hex) t0_operating_mode[2:0] t0_operating_mode_cnfg 53 t4_operating_mode[2:0] t4_operating_mode_cnfg 54 t0_dpll_operating_mod e[2:0] operating_sts 52 t0_dpll_lock t0_operating_mode 1 interrupts2_sts 0e t0_operating_mode 2 interrupts2_enable_cnfg 11 t0_for_t4 t4_input_sel_cnfg 51
IDT82V3285 wan pl l functional description 32 december 9, 2008 3.10 t0 / t4 dpll operating mode the t0/t4 dpll gives a stable performance in different applications without being affected by operating co nditions or silicon process varia- tions. it integrates a pfd (phase & frequency detector), a lpf (low pass filter) and a dco (digital cont rolled oscillator), which form a closed loop. if no input clock is selected, the loop is not closed, and the pfd and lpf do not function. the pfd detects the phase error, including the fast loss, coarse phase loss and fine phase loss (refer to chapter 3.7.1.1 fast loss to chapter 3.7.1.3 fine phase loss ). the averaged phase error of the t0/ t4 dpll feedback with respect to the selected input clock is indicated by the current_ph_data[15:0] bits . it can be calculated as follows: averaged phase error (ns) = current_ph_data[15:0] x 0.61 the lpf filters jitters. its 3 db bandwidth and damping factor are pro- grammable. a range of bandwidth s and damping factors can be set to meet different application requirem ents. generally, the lower the damp- ing factor is, the longer the locking time is and the more the gain is. the dco controls the dpll output. the frequency of the dpll out- put is always multiplied on the basis of the master clock. the phase and frequency offset of the dpll output may be locked to those of the selected input clock. the current frequency offset with respect to the master clock is indicated by t he current_dpll_freq[23:0] bits, and can be calculated as follows: current frequency offset (ppm ) = current_dpll_freq[23:0] x 0.000011 3.10.1 t0 dpll operating mode the t0 dpll loop is closed exc ept in free-run mode and holdover mode. for a closed loop, different bandw idths and damping factors can be used depending on dpll locking stages: starting, acquisition and locked. in the first two seconds when the t0 dpll attempts to lock to the selected input clock, the starti ng bandwidth and damping factor are used. they are set by the t0_dpll_start_bw[4:0] bits and the t0_dpll_start_damping[2:0] bits respectively. during the acquisition, the ac quisition bandwidth and damping factor are used. they are set by the t0_dpll_acq_bw[4:0] bits and the t0_dpll_acq_damping[2:0] bits respectively. when the t0 selected input clock is locked, the locked bandwidth and damping factor are used. they are set by the t0_dpll_locked_bw[4:0] bits and the t0_dpll_locked_damping[2:0] bits respectively. the corresponding bandwidth and damping factor are used when the t0 dpll operates in different dpll locking stages: starting, acquisition and locked, as controlled by the device automatically. only the locked bandwidth and damping factor can be used regard- less of the t0 dpll locking stage, as controlled by the auto_bw_sel bit. 3.10.1.1 free-run mode in free-run mode, the t0 dpll output refers to the master clock and is not affected by any input clock. the accuracy of the t0 dpll out- put is equal to that of the master clock. 3.10.1.2 pre-locked mode in pre-locked mode, the t0 dpll output attempts to track the selected input clock. the pre-locked mode is a secondary, temporary mode. 3.10.1.3 locked mode in locked mode, the t0 selected input clock is locked. the phase and frequency offset of the t0 dpll output track those of the t0 selected input clock. in this mode, if the t0 selected input clock is in fast loss status and the fast_los_sw bit is ?1?, the t0 dpll is unlocked (refer to chapter 3.7.1.1 fast loss ) and will enter lost-phase mode when the operating mode is switched automatically ; if the t0 selected input clock is in fast loss status and the fast_los_sw bit is ?0?, the t0 dpll lock- ing status is not affected and the t0 dpll will enter temp-holdover mode automatically. 3.10.1.3.1 temp-holdover mode the t0 dpll will automatically enter temp-holdover mode with a selected input clock switch or no qual ified input clock available when the operating mode switch is under external control. in temp-holdover mode, the t0 dpll has temporarily lost the selected input clock. the t0 dp ll operation in temp-holdover mode and that in holdover mode are alike (refer to chapter 3.10.1.5 holdover mode ) except the frequency offset acquiring methods. see chapter 3.10.1.5 holdover mode for details about the methods. the method is selected by the temp _holdover_mode[1:0] bits, as shown in table 18 : the device automatically controls the t0 dpll to exit from temp- holdover mode. 3.10.1.4 lost-phase mode in lost-phase mode, the t0 dpll output attempts to track the selected input clock. the lost-phase mode is a secondary, temporary mode. 3.10.1.5 holdover mode in holdover mode, the t0 dpll resorts to the stored frequency data acquired in locked mode to control its output. the t0 dpll output is not table 18: frequency offset co ntrol in temp-holdover mode temp_holdover_mode[1:0] freque ncy offset acquiring method 00 the same as that used in holdover mode 01 automatic instantaneous 10 automatic fast averaged 11 automatic slow averaged
IDT82V3285 wan pl l functional description 33 december 9, 2008 phase locked to any input clock. the frequency offset acquiring method is selected by the man_holdover bit, the auto_avg bit and the fast_avg bit, as shown in table 19 : 3.10.1.5.1 automatic instantaneous by this method, the t0 dpll freezes at the operating frequency when it enters holdover mode. the accuracy is 4.4x10 -8 ppm. 3.10.1.5.2 automatic slow averaged by this method, an internal iir (i nfinite impulse response) filter is employed to get the frequency offset. the iir filter gives a 3 db attenua- tion point corresponding to a period of 110 minutes. the accuracy is 1.1x10 -5 ppm. 3.10.1.5.3 automatic fast averaged by this method, an internal iir (i nfinite impulse response) filter is employed to get the frequency offset. the iir filter gives a 3 db attenua- tion point corresponding to a period of 8 minutes. the accuracy is 1.1x10 -5 ppm. 3.10.1.5.4 manual by this method, the frequency offset is set by the t0_holdover_freq[23:0] bits. the accuracy is 1.1x10 -5 ppm. the frequency offset of the t0 dpll output is indicated by the current_dpll_freq[23:0] bits. the device provides a reference for the value to be written to the t0_holdover_freq[23:0] bits. the value to be written can refer to the value read from the current _dpll_freq[23:0] bits or the t0_holdover_freq[23:0] bits (refer to chapter 3.10.1.5.5 holdover frequency offset read ); or then be processed by external software fil- tering. 3.10.1.5.5 holdover frequency offset read the offset value, which is ac quired by automatic slow averaged, automatic fast averaged and is set by related register bits, can be read from the t0_holdover_freq[23:0] bits by setting the read_avg bit and the fast_avg bit, as shown in table 20 . the frequency offset in ppm is calculated as follows: holdover frequency offset (ppm) = t0_holdover_freq[23:0] x 0.000011 3.10.1.6 pre-locked2 mode in pre-locked2 mode, the t0 dpll output attempts to track the selected input clock. the pre-locked2 mode is a secondary, temporary mode. 3.10.2 t4 dpll operating mode the t4 path is simpler compared with the t0 path. 3.10.2.1 free-run mode in free-run mode, the t4 dpll output refers to the master clock and is affected by any input clock. the accuracy of the t4 dpll output is equal to that of the master clock. 3.10.2.2 locked mode in locked mode, the t4 selected input clock may be locked in the t4 dpll. when the t4 selected input clock is locked, the phase and frequency offset of the t4 dpll output track those of the t4 selected input clock; when unlocked, the phase and frequency offset of the t4 dpll output attempt to track those of the selected input clock. the t4 dpll loop is closed in locked mode. its bandwidth and damping factor are set by the t4_dpll_locked_bw[1:0] bits and the t4_dpll_locked_damping[2:0 ] bits respectively. 3.10.2.3 holdover mode in holdover mode, the t4 dpll resorts to the stored frequency data acquired in locked mode to control its output. the t4 dpll output is not table 19: frequency offset control in holdover mode man_holdover auto_avg fast_avg fr equency offset acquiring method 0 0 don?t-care automatic instantaneous 1 0 automatic slow averaged 1 automatic fast averaged 1 don?t-care manual table 20: holdover fr equency offset read read_avg fast_avg offset value read from t0_holdover_freq[23:0] 0 don?t-care the value is equal to the one written to. 1 0 the value is acquired by automatic slow averaged method, not equal to the one written to. 1 the value is acquired by automatic fast averaged method, not equal to the one written to.
IDT82V3285 wan pl l functional description 34 december 9, 2008 phase locked to any input clock. t he t4 dpll freezes at the operating frequency when it enters holdover mode. the accuracy is 4.4x10 -8 ppm. table 21: related bit / register in chapter 3.10 bit register address (hex) current_ph_data[15:0] c urrent_dpll_phase[15:8]_ sts, current_dpll_phase[7:0]_sts 69 *, 68 * current_dpll_freq[23:0] current_dpll_freq[23:16]_sts, current_dpll_freq[15:8]_sts, current_dpll_freq[7:0]_sts 64 *, 63 *, 62 * t0_dpll_start_bw[4:0] t0_dpll_start_bw_damping_cnfg 56 t0_dpll_start_damping[2:0] t0_dpll_acq_bw[4:0] t0_dpll_acq_bw_damping_cnfg 57 t0_dpll_acq_damping[2:0] t0_dpll_locked_bw[4:0] t0_dpll_locked_bw_damping_cnfg 58 t0_dpll_locked_damping[2:0] auto_bw_sel t0_bw_overshoot_cnfg 59 fast_los_sw phase_loss_fine_limit_cnfg 5b * temp_holdover_mode[1:0] t0_holdover_mode_cnfg 5c man_holdover auto_avg fast_avg read_avg t0_holdover_freq[23:0] t0_holdover_freq[23:16]_cnfg, t0_holdover_freq[15:8]_cnfg, t0_holdover_freq[7:0]_cnfg 5f, 5e, 5d t4_dpll_locked_bw[1:0] t4_dpll_locked_bw_damping_cnfg 61 t4_dpll_locked_damping[2:0] t4_t0_sel t4_t0_reg_sel_cnfg 07 note: * the setting in the 5b, 62 ~ 64, 68 and 69 registers is either for t0 path or for t4 path, as determined by the t4_t0_sel bit.
IDT82V3285 wan pl l functional description 35 december 9, 2008 3.11 t0 / t4 dpll output the dpll output is locked to the se lected input clock. according to the phase-compared result of the feedback and the selected input clock, and the dpll output frequency offset, the pfd output is limited and the dpll output is frequency offset limited. 3.11.1 pfd output limit the pfd output is limited to be within 1 ui or within the coarse phase limit (refer to chapter 3.7.1.2 coarse phase loss ), as determined by the multi_ph_app bit. 3.11.2 frequency offset limit the dpll output is limited to be wi thin the dpll hard limit (refer to chapter 3.7.1.4 hard limit exceeding ). for t0 dpll, the integral path value can be frozen when the dpll hard limit is reached. this function, enabled by the t0_limt bit, will min- imize the subsequent overshoot when t0 dpll is pulling in. 3.11.3 pbo (t0 only) the pbo function is only supported by the t0 path. when a pbo event is triggered, the phase offset of the selected input clock with respect to the t0 dpll output is measured. the device then automatically accounts for the m easured phase offset and compensates an appropriate phase offset into the dpll output so that the phase tran- sients on the t0 dpll output are minimized. a pbo event is triggered if an y one of the following conditions occurs: ? t0 selected input clock switches (the pbo_en bit is ?1?); ? t0 dpll exits from holdover mode or free-run mode (the pbo_en bit is ?1?); ? phase-time changes on the t0 selected input clock are greater than a programmable limit over an interval of less than 0.1 sec- onds (the ph_mon_pbo_en bit is ?1?). for the first two conditions, the phase transients on the t0 dpll out- put are minimized to be no more than 0.61 ns with pbo. the pbo can also be frozen at the current phase offset by setting the pbo_frez bit. when the pbo is frozen, the device will ignore any further pbo events triggered by the above two conditi ons, and maintain the current phase offset. when the pbo is disabled, there may be a phase shift on the t0 dpll output and the t0 dpll output tracks back to 0 degree phase off- set with respect to the t0 selected input clock. the last condition is specially fo r stratum 2 and 3e clocks. the pbo requirement specified in the telc ordia gr-1244-core is: ?input phase- time changes of 3.5 s or greater ov er an interval of less than 0.1 sec- onds or less shall be built-out by st ratum 2 and 3e clocks to reduce the resulting clock phase-time chan ge to less than 50 ns. phase-time changes of 1.0 s or less over an in terval of 0.1 seconds shall not be built-out.? based on this requirement, phase-time changes of more than 1.0 s but less than 3.5 s that occur over an interval of less than 0.1 seconds may or may not be built-out. an integrated phase transient monitor can be enabled by the ph_mon_en bit to monitor the phas e-time changes on the t0 selected input clock. when the phase-time c hanges are greater than a limit over an interval of less than 0.1 sec onds, a pbo event is triggered and the phase transients on the dpll output are absorbed. the limit is pro- grammed by the ph_tr_mon_limt[3 :0] bits, and can be calculated as follows: limit (ns) = (ph_tr_mon_limt[3:0] + 7) x 156 the phase offset induced by pbo will nev er result in a coarse or fine phase loss. 3.11.4 phase offset selection (t0 only) the phase offset of the t0 selected input clock with respect to the t0 dpll output can be adjusted. if the dev ice is configured as the master, the ph_offset_en bit determines whether the input-to-output phase offset is enabled; if the device is configured as the slave, the input-to- output phase offset is always enabled. if enabled, the input-to-output phase offset can be adjusted by setting the ph_offset[9:0] bits. the input-to-output phase offset can be calculated as follows: phase offset (ns) = ph_offset[9:0] x 0.61 3.11.5 four paths of t0 / t4 dpll outputs the t0 dpll output and the t4 dpll output are phase aligned with the t0 selected input clock and the t4 selected input clock respectively every 125 s period. each dpll has four output paths. 3.11.5.1 t0 path the four paths for t0 dpll output are as follows: ? 77.76 mhz path - outputs a 77.76 mhz clock; ? 16e1/16t1 path - outputs a 16e1 or 16t1 clock, as selected by the in_sonet_sdh bit; ? gsm/obsai/16e1/16t1 path - outputs a gsm, obsai, 16e1 or 16t1 clock, as selected by the t0_gsm_obsai_16e1_16t1_ sel[1:0 ] bits; ? 12e1/24t1/e3/t3 path - outputs a 12e1, 24t1, e3 or t3 clock, as selected by the t0_12e1_24t1_e3_t3_sel[1:0] bits. t0 selected input clock is compared with a t0 dpll output for dpll locking. the output can only be deriv ed from the 77.76 mhz path or the 16e1/16t1 path. the output path is automatically selected and the out- put is automatically divided to get the same frequency as the t0 selected input clock. the t0 dpll 77.76 mhz output or an 8 khz signal derived from it can be provided for the t4 dpll i nput clock selection (refer to chapter 3.6 t0 / t4 dpll input clock selection ). t0 dpll outputs are provided for t0/t4 apll or device output pro- cess.
IDT82V3285 wan pl l functional description 36 december 9, 2008 3.11.5.2 t4 path the four paths for t4 dpll output are as follows: ? 77.76 mhz path - outputs a 77.76 mhz clock; ? 16e1/16t1 path - outputs a 16e1 or 16t1 clock, as selected by the in_sonet_sdh bit; ? gsm/gps/16e1/16t1 path - outputs a gsm, gps, 16e1 or 16t1 clock, as selected by the t4_gsm_gps_16e1_16t1_ sel[1:0] bits; ? 12e1/24t1/e3/t3 path - outputs a 12e1, 24t1, e3 or t3 clock, as selected by the t4_12e1_24t1_e3_t3_sel[1:0] bits. t4 selected input clock is compared with a t4 dpll output for dpll locking. the output can be derived from the 77.76 mhz path or the 16e1/16t1 path. in this case, the output path is automatically selected and the output is automatically divided to get the same frequency as the t4 selected input clock. in addition, t4 selected input clock is compared with the t0 selected input clock to get the phase differ ence between t0 and t4 selected input clocks, as determined by the t4_test_t0_ph bit. t4 dpll outputs are provided for t0/t4 apll or device output pro- cess. table 22: related bit / register in chapter 3.11 bit register address (hex) multi_ph_app phase_loss_coarse_limit_cnfg 5a * t0_limt t0_bw_overshoot_cnfg 59 pbo_en mon_sw_pbo_cnfg 0b pbo_frez ph_mon_pbo_en phase_mon_pbo_cnfg 78 ph_mon_en ph_tr_mon_limt[3:0] ph_offset_en phase_offset[9:8]_cnfg 7b ph_offset[9:0] phase_offset[9:8]_cn fg, phase_offset[7:0]_cnfg 7b, 7a in_sonet_sdh input_mode_cnfg 09 t0_gsm_obsai_16e 1_16t1_sel[1:0] t0_dpll_apll_path_cnfg 55 t0_12e1_24t1_e3_t3_sel[1:0] t4_gsm_gps_16e1_16t1_sel[1:0] t4_dpll_apll_path_cnfg 60 t4_12e1_24t1_e3_t3_sel[1:0] t4_test_t0_ph t4_input_sel_cnfg 51 t4_t0_sel t4_t0_reg_sel_cnfg 07 note: * the setting in the 5a register is either for t0 pat h or for t4 path, as determined by the t4_t0_sel bit.
IDT82V3285 wan pl l functional description 37 december 9, 2008 3.12 t0 / t4 apll a t0 apll and a t4 apll are provided for a better jitter and wander performance of the device output clocks. the bandwidths of the t0/t4 apll are set by the t0_apll_bw[1:0] / t4_apll_bw[1:0] bits respectively. the lower the bandwidth is, the better the jitter and wander performance of the t0/t4 apll output are. the input of the t0/t4 apll can be derived from one of the t0 and t4 dpll outputs, as selected by the t0_apll_path[3:0] / t4_apll_path[3:0] bits respectively. both the apll and dpll outputs are provided for selection for the device output. 3.13 output clocks & frame sync signals the device supports 5 output cloc ks and 2 frame sync output signals altogether. 3.13.1 output clocks the device provides 5 output clocks. according to the output port technology, the output ports support the following technologies: ? pecl/lvds; ? cmos. out1 ~ out3 output cmos signals. out4 and out5 output pecl or lvds signals, as selected by the out4_pecl_lvds bit and the out 5_pecl_lvds bit respectively. the outputs on out1 ~ out5 are variable, depending on the signals derived from the t0/t4 dpll and t0/t4 apll outputs, and the corre- sponding outn_path_sel[3:0] bits (1 n 5). the derived signal can be from the t0/t4 dpll and t0/t4 apll outputs, as selected by the corresponding outn_path_sel[3:0] bits (1 n 5). if the signal is derived from one of the t0/t4 dpll outputs, please refer to table 24 for the output frequency. if the signal is derived from the t0/t4 apll output, please refer to table 25 for the output frequency. the outputs on out1 to out5 can be inverted, as determined by the corresponding outn_inv bit (1 n 5). all the output clocks derived from t0/t4 selected input clock are aligned with the t0/t4 selected i nput clock respectively every 125 s period. table 23: related bit / register in chapter 3.12 bit register address (hex) t0_apll_bw[1:0] t0_t4_apll_bw_cnfg 6a t4_apll_bw[1:0] t0_apll_path[3:0] t0_dpll_apll_path_cnfg 55 t4_apll_path[3:0] t4_dpll_apll_path_cnfg 60 table 24: outputs on out1 ~ out5 if derived from t0/t4 dpll outputs outn_divider[3:0] (output divider) 1 outputs on out1 ~ out5 if derived from t0/t4 dpll outputs 2 77.76 mhz 12e1 16e1 24t1 16t1 e3 t3 gsm (26 mhz) obsai (30.72 mhz) gps (40 mhz) 0000 output is disabled (output low). 0001 0010 12e1 16e1 24t1 16t1 e3 t3 0011 6e1 8e1 12t1 8t1 13 mhz 15.36 mhz 20 0100 3e1 4e1 6t1 4t1 10 0101 2e1 4t1 0110 2e1 3t1 2t1 5 0111 e1 2t1 1000 e1 t1 1001 t1 1010 64 khz 1011 8 khz 1100 2 khz 1101 400 hz 1110 1hz 1111 output is disabled (output high). note: 1. 1 n 5. each output is assigned a frequency divider . 2. e1 = 2.048 mhz, t1 = 1.544 mhz, e3 = 34.368 mhz, t3 = 44.736 mhz. the blank cell means the configuration is reserved.
IDT82V3285 wan pl l functional description 38 december 9, 2008 table 25: outputs on out1 ~ out5 if derived from t0/t4 apll outn_divider[3:0] (output divider) 1 outputs on out1 ~ out5 if derived from t0/t4 apll output 2 77.76 mhz x 4 12e1 x 4 16e1 x 4 24t1 x 4 16t1 x 4 e3 t3 gsm (26 mhz x 2) obsai (30.72 mhz x 10) gps (40 mhz) 0000 output is disabled (output low). 0001 622.08 mhz 3 0010 311.04 mhz 3 48e1 64e1 96t1 64t1 e3 t3 52 mhz 0011 155.52 mhz 24e1 32e1 48t1 32t1 26 mhz 153.6 mhz 20 mhz 0100 77.76 mhz 12e1 16e1 24t1 16t1 13 mhz 76.8 mhz 10 mhz 0101 51.84 mhz 8e1 16t1 0110 38.88 mhz 6e1 8e1 12t1 8t1 38.4 mhz 5 mhz 0111 25.92 mhz 4e1 8t1 1000 19.44 mhz 3e1 4e1 6t1 4t1 1001 2e1 4t1 61.44 mhz 4 1010 2e1 3t1 2t1 30.72 mhz 4 1011 6.48 mhz e1 2t1 15.36 mhz 4 1100 e1 t1 7.68 mhz 4 1101 t1 3.84 mhz 4 1110 1111 output is disabled (output high). note: 1. 1 n 5. each output is assigned a frequency divider. 2. in the apll, the selected t0/t4 dpll output may be multiplied. e1 = 2.048 mhz, t1 = 1.544 mhz, e3 = 34.368 mhz, t3 = 44.736 mhz. the blank cell means the configuration is reserved. 3. the 622.08 mhz and 311.04 mhz differential signals are only output on out4 and out5. 4. the 61.44 mhz, 30.72 mhz, 15.36 mhz, 7.68 mhz and 3.84 mhz outputs are only derived from t0 apll.
IDT82V3285 wan pl l functional description 39 december 9, 2008 3.13.2 frame sync output signals an 8 khz and a 2 khz frame sync signals are output on the frsync_8k and mfrsync_2k pins if enabled by the 8k_en and 2k_en bits respectively. they are cmos outputs. the two frame sync signals are deriv ed from the t0 apll output and are aligned with the output clock. t hey can be synchronized to the frame sync input signal. if the frame sync input signal with respect to the t0 selected input clock is above a limit set by the sync_mon_limt[2:0] bits, an external sync alarm will be raised and ex_sync1 is disabled to synchronize the frame sync output signals. the ex ternal sync alarm is cleared once ex_sync1 with respect to the t0 sele cted input clock is within the limit. if it is within the limit, whether ex_sync1 is enabled to synchronize the frame sync output signal is det ermined by the auto_ext_sync_en bit and the ext_sync_en bit. refer to table 26 for details. when the frame sync input signal is enabled to synchronize the frame sync output signal, it should be adj usted to align itself with the t0 selected input clock. nominally, the falling edge of ex_sync1 is aligned with the rising edge of the t0 selected input clock. ex_sync1 may be 0.5 ui early/late or 1 ui late due to the circuit and board wiring delays. setting the sampling of ex_sync1 by the sync_ph1[1:0] bits will compensate this early/late. refer to figure 9 to figure 12 . the ex_sync_alarm_mon bit indi cates whether ex_sync1 is in external sync alarm status. the exter nal sync alarm is indicated by the ex_sync_alarm 1 bit. if the ex_sync_alarm 2 bit is ?1?, the occur- rence of the external sync alarm will trigger an interrupt. the 8 khz and the 2 khz frame sync output signals can be inverted by setting the 8k_inv and 2k_inv bits respectively. the frame sync out- puts can be 50:50 duty cycle or pulsed, as determined by the 8k_pul and 2k_pul bits respectively. when t hey are pulsed, the pulse width is defined by the period of out1; and they are pulsed on the position of the falling or rising edge of the st andard 50:50 duty cycle, as selected by the 2k_8k_pul_position bit. figure 9. on target frame sync input signal timing figure 10. 0.5 ui early frame sync input signal timing table 26: synchronization control auto_ext_sync_en ext_ sync_en synchronization don?t-care 0 disabled 01 enabled 1 1 enabled if the t0 selected input clock is in5; otherwise, disabled. t0 selected input clock output clocks ex_sync1 frame sync output signals t0 selected input clock output clocks ex_sync1 frame sync output signals
IDT82V3285 wan pl l functional description 40 december 9, 2008 figure 11. 0.5 ui late fram e sync input signal timing figure 12. 1 ui late frame sync input signal timing t0 selected input clock output clocks ex_sync1 frame sync output signals t0 selected input clock output clocks ex_sync1 frame sync output signals table 27: related bit / register in chapter 3.13 bit register address (hex) out4_pecl_lvds differential_in_out_osci_cnfg 0a out5_pecl_lvds outn_path_sel[3:0] (1 n 5) out1_freq_cnfg ~ out5_freq_cnfg 6d ~ 71 outn_divider[3:0] (1 n 5) in_sonet_sdh input_mode_cnfg 09 auto_ext_sync_en ext_sync_en 8k_en fr_mfr_sync_cnfg 74 2k_en 8k_inv 2k_inv 8k_pul 2k_pul 2k_8k_pul_position sync_mon_limt[2:0] sync_monitor_cnfg 7c sync_ph1[1:0] sync_phase_cnfg 7d ex_sync_alarm_mon operating_sts 52 ex_sync_alarm 1 interrupts3_sts 0f ex_sync_alarm 2 interrupts3_enable_cnfg 12
IDT82V3285 wan pl l functional description 41 december 9, 2008 3.14 master / slave configuration master / slave configuration is only supported by the t0 path of the device. two devices should be used together in order to: ? enable system protection agai nst single chip failure; ? guarantee no service interrupt during system maintenance, such as software or hardware upgrade. of the two devices, one is configur ed as the master and the other is configured as the slave. the conf iguration is made by the ms/ sl pin and the ms_sl_ctrl bit (b0, 13h), as shown in table 28 : in this application, all the output clocks derived from the t0 selected input clock and the frame sync output signals from the two devices are at the same frequency offset and phase. refer to chapter 3.13.2 frame sync output signals for details. the difference between the master and the slave is: in the master, the in5 should not be selected by the t0 dpll; in the slave, the follow- ing functions are automatically forced: ? the t0 selected input clock is in5; ? t0 pbo is disabled; ? t0 dpll operates at the acquisition bandwidth and damping fac- tor; ? ex_sync1 is used for synchronization; ? t0 dpll operates in locked mode. in the slave, the corresponding registers of the above forced func- tions can still be configured, but t heir configuration does not take any effect. the frequency of the t0 selected input clock in5 is recommended to be 6.48 mhz. figure 13. physical connection between two devices table 28: device master / slave control master / slave control result ms/ sl pin ms_sl_ctrl bit high 0master 1slave low 0slave 1master ms/ sl one output clock hardware control in1 in2 in5 in3 one output frame sync signal out1 frsync_8k/ mfrsync_2k out5 . . . ms/ sl in1 in2 in5 in3 out1 frsync_8k/ mfrsync_2k out5 . . . backplane connections ex_sync1 ex_sync1 chip a backplane backplane chip b in4 in4 one output clock one output frame sync signal
IDT82V3285 wan pl l functional description 42 december 9, 2008 3.15 interrupt summary the interrupt sources of the device are as follows: ? t4 dpll locking status change ? input clocks for t0 path validity change ? t0 selected input clock fail ? no qualified input clock for t4 path is available ? t0 dpll operating mode switch ? external sync alarm all of the above interrupt events are indicated by the corresponding interrupt status bit. if the corresponding interrupt enable bit is set, any of the interrupts can be reported by t he int_req pin. the output charac- teristics on the int_req pin are determined by the hz_en bit and the int_pol bit. interrupt events are cleared by writing a ?1? to the corresponding interrupt status bit. the int_req pin will be inactive only when all the pending enabled interrupts are cleared. in addition, the interrupt of t0 selected input clock fail can be reported by the tdo pin, as det ermined by the los_flag_to_tdo bit. 3.16 t0 and t4 summary the main features supported by the t0 path are as follows: ? phase lock alarm; ? forced or automatic input clock selection/switch; ? 3 primary and 3 secondary, temporary dpll operating modes, switched automatically or under external control; ? automatic switch between starting, acquisition and locked band- widths/damping factors; ? programmable dpll bandwidths from 0.5 mhz to 560 hz in 19 steps; ? programmable damping factors: 1.2, 2.5, 5, 10 and 20; ? fast loss, coarse phase loss, fine phase loss and hard limit exceeding monitoring; ? output phase and frequency offset limited; ? automatic instantaneous, automatic slow averaged, automatic fast averaged or manual holdover frequency offset acquiring; ? pbo to minimize output phase transients; ? programmable output phase offset; ? low jitter multiple clock outputs with programmable polarity; ? low jitter 2 khz and 8 khz frame sync signal outputs with pro- grammable pulse width and polarity; ? master / slave application to enable system protection against single device failure. the main features supported by the t4 path are as follows: ? forced or automatic input clock selection/switch; ? locking to t0 dpll output; ? 3 dpll operating modes, switched automatically or under exter- nal control; ? programmable dpll bandwidth: 18 hz, 35 hz, 70 hz and 560 hz; ? programmable damping factor: 1.2, 2.5, 5, 10 and 20; ? fast loss, coarse phase loss, fine phase loss and hard limit exceeding monitoring; ? output phase and frequency offset limited; ? automatic instantaneous holdover frequency offset; ? low jitter multiple clock outputs with programmable polarity. table 29: related bit / register in chapter 3.15 bit register address (hex) hz_en interrupt_cnfg 0c int_pol los_flag_to_tdo mon_sw_pbo_cnfg 0b
IDT82V3285 wan pl l functional description 43 december 9, 2008 3.17 power supply fi ltering techniques figure 14. IDT82V3285 power decoupling scheme to achieve optimum jitter perfo rmance, power supply filtering is required to minimize supply noise m odulation of the output clocks. the common sources of power supply noi se are switch power supplies and the high switching noise from the outputs to the internal pll. the IDT82V3285 provides separate vdda pow er pins for the internal analog pll, vdd_diff for the differential output driver circuit and vddd pins for the core logic as well as i/o driver circuits. to minimize switching power supp ly noise generated by the switch- ing regulator, the power supply output should be filtering with sufficient bulk capacity to minimize ripple and 0.1 uf (0402 case size, ceramic) caps to filter out the switching transients. for the IDT82V3285, the decoupling for vdda, vdd_diff and vddd are handled individually. vddd , vdd_diff and vdda should be individually connected to the pow er supply plane through vias, and bypass capacitors should be used for each pin. figure 14 illustrated how bypass capacitor and ferrite bead s hould be connected to power pins. the analog power supply vdda an d vdd_diff should have low impedance. this can be achieved by using one 10 uf (1210 case size, ceramic) and at least four 0.1 uf ( 0402 case size, ceramic) capacitors in parallel. the 0.1 uf (0402 case si ze, ceramic) capacitors must be placed right next to the vdda and vd d_diff pins as close as possible. note that the 10 uf capacitor must be of 1210 case size, and it must be ceramic for lowest esr (effective series resistance) possible. the 0.1 uf should be of case size 0402, this offers the lowest esl (effective series inductance) to achieve low impedance towards the high speed range. for vddd, at least ten 0.1 uf (0402 case size, ceramic) and one 10 uf (1210 case size, ceramic) c apacitors are recommended. the 0.1 uf capacitors should be placed as close to the vddd pins as possible. please refer to evaluation board schematic for details. IDT82V3285 3.3v 0.1 f 10 f dgnd agnd gnd_diff 1, 5, 20, 92 vdda vddd 0.1 f 10 f 32, 38 11, 14, 15, 29, 62, 84, 87 6, 19, 91 vdd_diff 33, 39 12, 13, 16, 26, 50, 61, 85, 86 0. 1 f 0.1 f0.1 f 0.1 f 0.1 f0.1 f0.1 f 0.1 f 0. 1 f0.1 f0.1 f slf7028t-100m1r1 slf7028t-100m1r1 3.3v
IDT82V3285 wan pl l typical application 44 december 9, 2008 4 typical application the device supports master / sl ave application, as shown in figure 15 : figure 15. typical application 4.1 master / slave application master / slave application is only supported by the t0 path of the device. in master / slave application, tw o devices should be used together. of the two devices, one is configured as the master and the other is con- figured as the slave. refer to chapter 3.14 master / slave configuration for details. bits/ssu timing module stratum 2/3e idt82v3288 bits/ssu timing module stratum 2/3e idt82v3288 prs (primary reference source) stratum 2/3e/3/smc/sec module IDT82V3285 stratum 2/3e/3/smc/sec module IDT82V3285 line timing line timing master/slave typical 19.44 mhz and other oc-n clock 155.52 mbit/s line card idt82v3255 622.08 mbit/s line card idt82v3255 2.5 gbit/s line card idt82v3255 10 gbit/s line card idt82v3255 central clock modules typical 8 khz/1.544 mhz/2.048 mhz sdh/sonet or other equipment timing system typical 19.44 mhz and other oc-n clock typical 19.44 mhz and other oc-n clock typical 19.44 mhz and other oc-n clock . . . . . .
IDT82V3285 wan pl l microprocessor interface 45 december 9, 2008 5 microprocessor interface the microprocessor interface provi des access to read and write the registers in the device. the microprocessor interface supports the fol- lowing five modes: ? eprom mode; ? multiplexed mode; ? intel mode; ? motorola mode; ? serial mode. the microprocessor interface mode is selected by the mpu_sel_cnfg[2:0] bits (b2~0, 7fh) . the interface pins in different interface modes are listed in table 30 : table 30: microprocessor interface mpu_sel_cnfg[2:0] bits microprocessor interface mode interface pins 001 erpom cs , a[6:0], ad[7:0] 010 multiplexed cs , ale, wr , rd , ad[7:0], rdy 011 intel cs , wr , rd , a[6:0], ad[7:0], rdy 100 motorola cs , wr , a[6:0], ad[7:0], rdy 101 serial cs , sclk, sdi, sdo, clke
IDT82V3285 wan pl l microprocessor interface 46 december 9, 2008 5.1 eprom mode in this mode, the device is used with an eprom. the configuration data will be automatically read from the eprom after the device is pow- ered on. figure 16. eprom access timing diagram table 31: access timing characteristics in eprom mode symbol parameter min typ max unit t acc cs to valid data delay time 920 ns t acc cs address data a[6:0] ad[7:0] high-z high-z
IDT82V3285 wan pl l microprocessor interface 47 december 9, 2008 5.2 multiplexed mode figure 17. multiplexed read timing diagram table 32: read timing charact eristics in multiplexed mode symbol parameter min typ max unit t one cycle time of the master clock 12.86 ns t in delay of input pad 5 ns t out delay of output pad 5 ns t su1 valid address to ale falling edge setup time 2 ns t su2 valid cs to valid rd setup time 0 ns t d1 valid rd to valid data delay time 3.5t + 10 ns t d2 valid cs to valid rdy delay time 13 ns t d4 rd rising edge to ad[7:0] high impedance delay time 10 ns t d5 rd rising edge to rdy low delay time 13 ns t d6 cs rising edge to rdy release delay time 13 ns t pw1 valid rd pulse width low 4.5t + 10 * ns t pw2 valid rdy pulse width low 4.5t + 10 ns t pw3 valid ale pulse width high 2 ns t h1 valid address after ale falling edge hold time 3 ns t h2 valid cs after rd rising edge hold time 0 ns t h3 valid rd after rdy rising edge hold time 0 ns t t time between ale falling edge and rd falling edge 0 ns t ti time between consecutive read-read or read-write accesses ( rd rising edge to ale rising edge) >t ns note: * timing with rdy. if rdy is not used, t pw1 is 3.5t + 10. t pw3 ale wr ad[7:0] rdy t h2 rd address high-z high-z t t t su2 data t d1 t d4 t d2 t pw2 t d5 t su1 t pw1 t h1 t h3 cs t d6
IDT82V3285 wan pl l microprocessor interface 48 december 9, 2008 figure 18. multiplexed write timing diagram table 33: write timing charact eristics in multiplexed mode symbol parameter min typ max unit t one cycle time of the master clock 12.86 ns t in delay of input pad 5 ns t out delay of output pad 5 ns t su1 valid address to ale falling edge setup time 2 ns t su2 valid cs to valid wr setup time 0 ns t su3 valid data to wr rising edge setup time 3 ns t d2 valid cs to valid rdy delay time 13 ns t d5 wr rising edge to rdy low delay time 13 ns t d6 cs rising edge to rdy release delay time 13 ns t pw1 valid wr pulse width low 1.5t + 10 ns t pw2 valid rdy pulse width low 1.5t + 10 ns t pw3 valid ale pulse width high 2 ns t h1 valid address after ale falling edge hold time 3 ns t h2 valid cs after wr rising edge hold time 0 ns t h3 valid wr after rdy rising edge hold time 0 ns t h4 valid data after wr rising edge hold time 9 ns t t time between ale falling edge and wr falling edge 0 ns t ti time between consecutive write-read or write-write accesses ( wr rising edge to ale rising edge) >7t ns t pw3 ale wr ad[7:0] rdy t h2 rd address high-z high-z t t t su2 data t su3 t h4 t d2 t su1 t pw1 t h1 cs t pw2 t h3 t d5 t d6
IDT82V3285 wan pl l microprocessor interface 49 december 9, 2008 5.3 intel mode figure 19. intel read timing diagram table 34: read timing characteristics in intel mode symbol parameter min typ max unit t one cycle time of the master clock 12.86 ns t in delay of input pad 5 ns t out delay of output pad 5 ns t su1 valid address to valid cs setup time 0 ns t su2 valid cs to valid rd setup time 0 ns t d1 valid rd to valid data delay time 3.5t + 10 ns t d2 valid cs to valid rdy delay time 13 ns t d4 rd rising edge to ad[7:0] high impedance delay time 10 ns t d5 rd rising edge to rdy low delay time 13 ns t d6 cs rising edge to rdy release delay time 13 ns t pw1 valid rd pulse width low 4.5t + 10 * ns t pw2 valid rdy pulse width low 4.5t + 10 ns t h1 valid address after rd rising edge hold time 0 ns t h2 valid cs after rd rising edge hold time 0 ns t h3 valid rd after rdy rising edge hold time 0 ns t ti time between consecutive read-read or read-write accesses ( rd rising edge to rd falling edge, or rd rising edge to wr falling edge) >t ns note: * timing with rdy. if rdy is not used, t pw1 is 3.5t + 10. cs wr ad[7:0] rdy a[6:0] address high-z high-z t su1 t h1 t d4 t d1 t d2 t d5 t su2 t pw1 t h2 rd data t h3 t pw2 t d6 high-z high-z
IDT82V3285 wan pl l microprocessor interface 50 december 9, 2008 figure 20. intel write timing diagram table 35: write timing ch aracteristics in intel mode symbol parameter min typ max unit t one cycle time of the master clock 12.86 ns t in delay of input pad 5 ns t out delay of output pad 5 ns t su1 valid address to valid cs setup time 0 ns t su2 valid cs to valid wr setup time 0 ns t su3 valid data before wr rising edge setup time 3 ns t d2 valid cs to valid rdy delay time 13 ns t d5 wr rising edge to rdy low delay time 13 ns t d6 cs rising edge to rdy release delay time 13 ns t pw1 valid wr pulse width low 1.5t + 10 ns t pw2 valid rdy pulse width low 1.5t + 10 ns t h1 valid address after wr rising edge hold time 0 ns t h2 valid cs after wr rising edge hold time 0 ns t h3 valid wr after rdy rising edge hold time 0 ns t h4 valid data after wr rising edge hold time 9 ns t ti time between consecutive write-read or write-write accesses ( wr rising edge to wr falling edge, or wr rising edge to rd falling edge) >7t ns t su2 cs wr ad[7:0] a[6:0] t h1 rd address t su1 t pw1 t h2 data t su3 t h4 rdy high-z high-z t d2 t pw2 t h3 t d5 t d6
IDT82V3285 wan pl l microprocessor interface 51 december 9, 2008 5.4 motorola mode figure 21. motorola read timing diagram table 36: read timing characteristics in motorola mode symbol parameter min typ max unit t one cycle time of the master clock 12.86 t in delay of input pad 5 ns t out delay of output pad 5 ns t su1 valid address to valid cs setup time 0 ns t su2 valid wr to valid cs setup time 0 ns t d1 valid cs to valid data delay time 3.5t + 10 ns t d2 valid cs to valid rdy delay time 13 ns t d3 cs rising edge to ad[7:0] high impedance delay time 10 ns t d4 cs rising edge to rdy release delay time 13 ns t pw1 valid cs pulse width low 4.5t + 10 * ns t pw2 valid rdy pulse width high 4.5t + 10 ns t h1 valid address after cs rising edge hold time 0 ns t h2 valid wr after cs rising edge hold time 0 ns t h3 valid cs after rdy falling edge hold time 0 ns t r1 rdy release time 3 ns t ti time between consecutive read-read or read-write accesses ( cs rising edge to cs falling edge) > t ns note: * timing with rdy. if rdy is not used, t pw1 is 3.5t +10. cs wr ad[7:0] rdy a[6:0] address high-z high-z t pw1 t su2 t h2 t su1 t h1 t d3 t d1 t d2 t pw2 t d4 t h3 t r1 high-z high-z data
IDT82V3285 wan pl l microprocessor interface 52 december 9, 2008 figure 22. motorola write timing diagram table 37: write timing characteristics in motorola mode symbol parameter min typ max unit t one cycle time of the master clock 12.86 ns t in delay of input pad 5 ns t out delay of output pad 5 ns t su1 valid address to valid cs setup time 0 ns t su2 valid wr to valid cs setup time 0 ns t su3 valid data before cs rising edge setup time 3 ns t d2 valid cs to valid rdy delay time 13 ns t d4 cs rising edge to rdy release delay time 13 ns t pw1 valid cs pulse width low 1.5t + 10 ns t pw2 valid rdy pulse width high 1.5t + 10 ns t h1 valid address after valid cs rising edge hold time 0 ns t h2 valid wr after valid cs rising edge hold time 0 ns t h3 valid cs after rdy falling edge hold time 0 ns t h4 valid data after valid cs rising edge hold time 9 ns t r1 rdy release time 3 ns t ti time between consecutive write-write or write-read accesses ( cs rising edge to cs falling edge) > 7t ns cs wr ad[7:0] rdy a[6:0] address high-z high-z t pw1 t su2 t h2 t su1 t h1 t h4 t su3 t d2 t pw2 t d4 t h3 data t r1
IDT82V3285 wan pl l microprocessor interface 53 december 9, 2008 5.5 serial mode in a read operation, the active edge of sclk is selected by clke. when clke is asserted low, data on sdo will be clocked out on the ris- ing edge of sclk. when clke is asserted high, data on sdo will be clocked out on the falling edge of sclk. in a write operation, data on sdi will be clocked in on the rising edge of sclk. figure 23. serial read timing diagram (clke asserted low) figure 24. serial read timing diagram (clke asserted high) table 38: read timing characteristics in serial mode symbol parameter min typ max unit t one cycle time of the master clock 12.86 ns t in delay of input pad 5 ns t out delay of output pad 5 ns t su1 valid sdi to valid sclk setup time 4 ns t su2 valid cs to valid sclk setup time 14 ns t d1 valid sclk to valid data delay time 10 ns t d2 cs rising edge to sdo high impedance delay time 10 ns t pw1 sclk pulse width low 3.5t + 5 ns t pw2 sclk pulse width high 3.5t + 5 ns t h1 valid sdi after valid sclk hold time 6 ns t h2 valid cs after valid sclk hold time (clke = 0/1) 5 ns t ti time between consecutive read-read or read-write accesses ( cs rising edge to cs falling edge) 10 ns cs sclk sdi sdo high-z d0 d1 d2 d3 d4 d5 d6 d7 t pw2 t pw1 t su2 t su1 t h1 t h2 t d1 t d2 r/ w a0 a1 a2 a3 a4 a5 a6 cs sclk sdi sdo high-z r/ w a0 a1 a2 a3 a4 a5 a6 d0 d1 d2 d3 d4 d5 d6 d7 t d1 t d2 t h2
IDT82V3285 wan pl l microprocessor interface 54 december 9, 2008 figure 25. serial write timing diagram table 39: write timing char acteristics in serial mode symbol parameter min typ max unit t one cycle time of the master clock 12.86 ns t in delay of input pad 5 ns t out delay of output pad 5 ns t su1 valid sdi to valid sclk setup time 4 ns t su2 valid cs to valid sclk setup time 14 ns t pw1 sclk pulse width low 3.5t ns t pw2 sclk pulse width high 3.5t ns t h1 valid sdi after valid sclk hold time 6 ns t h2 valid cs after valid sclk hold time 5 ns t ti time between consecutive write-write or write-read accesses ( cs rising edge to cs falling edge) 10 ns cs sclk sdi sdo high-z r/ w a0 a1 a2 a3 a4 a5 a6 d0 d1 d2 d3 d4 d5 d6 d7 t su2 t su1 t h1 t h2 t pw2 t pw1
IDT82V3285 wan pl l jtag 55 december 9, 2008 6jtag this device is compliant with the ieee 1149.1 boundary scan stan- dard except the following: ? the output boundary scan cells do not capture data from the core and the device does not support extest instruction; ? the trst pin is set low by default and jtag is disabled in order to be consistent with other manufacturers. the jtag interface timing diagram is shown in figure 26 . figure 26. jtag interface timing diagram table 40: jtag timing characteristics symbol parameter min typ max unit t tck tck period 100 ns t s tms / tdi to tck setup time 25 ns t h tck to tms / tdi hold time 25 ns t d tck to tdo delay time 50 ns tck tdo tms tdi t tck t s t h t d
IDT82V3285 wan pl l programming information 56 december 9, 2008 7 programming information after reset, all the registers are set to their default values. the regis- ters are read or written via the microprocessor interface. before any write operation, the value in register protection_cnfg is recommended to be confirmed to make sure whether the write operation is enabled. the device provides 3 register protection modes: ? protected mode: no other register s can be written except register protection_cnfg itself; ? fully unprotected mode: all the writable registers can be written; ? single unprotected mode: one more register can be written besides register protection _cnfg. after write operation (not including writing a ?1? to clear a bit to ?0?), the device auto- matically switches to protected mode. writing ?0? to the registers will take no effect if the registers are cleared by writing ?1?. t0 and t4 paths share some registers, whose addresses are 27h, 28h, 2bh, 4eh, 4fh, 5ah, 5bh, 62h ~ 64h, 68h and 69h. the names of shared registers are marked with a *. before register read/write oper- ation, register t4_t0_reg_sel_cnfg is recommended to be con- firmed to make sure whether the register operation is available for t0 or t4 path. the access of the multi-word registers is different from that of the single-word registers. take the registers (04h, 05h and 06h) for an example, the write operation for the multi-word registers follows a fixed sequence. the register (04h) is conf igured first and the register (06h) is configured last. the three regist ers are configured continuously and should not be interrupted by any operat ion. the crystal calibration con- figuration will take effect after all the three registers are configured. dur- ing read operation, the register (04h) is read first and the register (06h) is read last. the crystal calibra tion reading should be continuous and not be interrupted by any operation. certain bit locations within the device register map are designated as reserved. to ensure proper and predi ctable operation, bits designated as reserved should not be written by the users. in addition, their value should be masked out from any testing or error detection methods that are implemented. 7.1 register map table 41 is the map of all the registers, sorted in an ascending order of their addresses. table 41: register list and map address (hex) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reference page global control registers 00 id[7:0] - device id 1 id[7:0] p 61 01 id[15:8] - device id 2 id[15:8] p 62 02 mpu_pin_sts - mpu_mode[2:0] pins status - - - - - mpu_pin_sts[2:0] p 62 04 nominal_freq[7:0]_cnfg - crys- tal oscillator frequency offset calibra- tion configuration 1 nominal_freq_value[7:0] p 62 05 nominal_freq[15:8]_cnfg - crys- tal oscillator frequency offset calibra- tion configuration 2 nominal_freq_value[15:8] p 62 06 nominal_freq[23:16]_cnfg - crystal oscillator frequency offset calibration configuration 3 nominal_freq_value[23:16] p 63 07 t4_t0_reg_sel_cnfg - t0 / t4 registers selection configuration --- t4_t0_se l ----p63 08 phase_alarm_time_out_cnfg - phase lock alarm time-out configu- ration multi_factor[1:0] time_out_value[5:0] p 64 09 input_mode_cnfg - input mode configuration auto_ex t_sync_ en ext_syn c_en ph_alar m_timeo ut sync_freq[1:0] in_sonet _sdh master_ slave revertiv e_mode p65 0a differential_in_out_osci_cnf g - differential input / output port & master clock configuration ----- osc_edg e out5_pe cl_lvds out4_pe cl_lvds p66
IDT82V3285 wan pl l programming information 57 december 9, 2008 0b mon_sw_pbo_cnfg - frequency monitor, input clock selection & pbo control freq_mo n_clk los_fla g_to_td o ultr_fas t_sw ext_sw pbo_fre z pbo_en - freq_mo n_hard_ en p67 13 ms_sl_ctrl_cnfg - master slave control ------- ms_sl_c trl p68 7e protection_cnfg - register pro- tection mode configuration protection_data[7:0] p 68 7f mpu_sel_cnfg - microprocessor interface mode configuration - - - - - mpu_sel_cnfg[2:0] p 69 interrupt registers 0c interrupt_cnfg - interrupt config- uration ------hz_enint_polp70 0d interrupts1_sts - interrupt status 1 - - in[4:1] - - p 70 0e interrupts2_sts - interrupt status 2 t0_oper ating_mo de t0_main_ ref_fail ed ---in5--p71 0f interrupts3_sts - interrupt status 3 ex_sync _alarm t4_sts - input_to _t4 ----p72 10 interrupts1_enable_cnfg - interrupt control 1 - - in[4:1] - - p 72 11 interrupts2_enable_cnfg - interrupt control 2 t0_oper ating_mo de t0_main_ ref_fail ed ---in5--p73 12 interrupts3_enable_cnfg - interrupt control 3 ex_sync _alarm t4_sts - input_to _t4 ----p73 input clock frequency & priority configuration registers 16 in1_cnfg - input clock 1 configura- tion direct_d iv lock_8k bucket_sel[1:0] in_freq[3:0] p 74 17 in2_cnfg - input clock 2 configura- tion direct_d iv lock_8k bucket_sel[1:0] in_freq[3:0] p 75 18 in3_in4_hf_div_cnfg - input clock 3 & 4 high frequency divider configu- ration in4_div[1:0] - - - - in3_div[1:0] p 76 19 in3_cnfg - input clock 3 configura- tion direct_d iv lock_8k bucket_sel[1:0] in_freq[3:0] p 77 1a in4_cnfg - input clock 4 configura- tion direct_d iv lock_8k bucket_sel[1:0] in_freq[3:0] p 78 1f in5_cnfg - input clock 5 configura- tion direct_d iv lock_8k bucket_sel[1:0] in_freq[3:0] p 79 23 pre_div_ch_cnfg - divn divider channel selection - - - - pre_div_ch_value[3:0] p 80 24 pre_divn[7:0]_cnfg - divn divider division factor configuration 1 pre_divn_value[7:0] p 80 25 pre_divn[14:8]_cnfg - divn divider division factor configuration 2 - pre_divn_value[14:8] p 81 27 in1_in2_sel_priority_cnfg - input clock 1 & 2 priority configuration * in2_sel_priority[3:0] in1_sel_priority[3:0] p 82 table 41: register list and map (continued) address (hex) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reference page
IDT82V3285 wan pl l programming information 58 december 9, 2008 28 in3_in4_sel_priority_cnfg - input clock 3 & 4 priority configuration * in4_sel_priority[3:0] in3_sel_priority[3:0] p 83 2b in5_sel_priority_cnfg - input clock 5 priority configuration * - - - - in5_sel_priority[3:0] p 84 input clock quality monitoring configuration & status registers 2e freq_mon_factor_cnfg - fac- tor of frequency monitor configuration - - - - freq_mon_factor[3:0] p 85 2f all_freq_mon_threshold_cn fg - frequency monitor threshold for all input clocks configuration - - - - all_freq_hard_threshold[3:0] p 85 31 upper_threshold_0_cnfg - upper threshold for leaky bucket configuration 0 upper_threshold_0_data[7:0] p 86 32 lower_threshold_0_cnfg - lower threshold for leaky bucket configuration 0 lower_threshold_0_data[7:0] p 86 33 bucket_size_0_cnfg - bucket size for leaky bucket configuration 0 bucket_size_0_data[7:0] p 86 34 decay_rate_0_cnfg - decay rate for leaky bucket configuration 0 ------ decay_rate_0_data [1:0] p87 35 upper_threshold_1_cnfg - upper threshold for leaky bucket configuration 1 upper_threshold_1_data[7:0] p 87 36 lower_threshold_1_cnfg - lower threshold for leaky bucket configuration 1 lower_threshold_1_data[7:0] p 87 37 bucket_size_1_cnfg - bucket size for leaky bucket configuration 1 bucket_size_1_data[7:0] p 88 38 decay_rate_1_cnfg - decay rate for leaky bucket configuration 1 ------ decay_rate_1_data [1:0] p88 39 upper_threshold_2_cnfg - upper threshold for leaky bucket configuration 2 upper_threshold_2_data[7:0] p 88 3a lower_threshold_2_cnfg - lower threshold for leaky bucket configuration 2 lower_threshold_2_data[7:0] p 89 3b bucket_size_2_cnfg - bucket size for leaky bucket configuration 2 bucket_size_2_data[7:0] p 89 3c decay_rate_2_cnfg - decay rate for leaky bucket configuration 2 ------ decay_rate_2_data [1:0] p89 3d upper_threshold_3_cnfg - upper threshold for leaky bucket configuration 3 upper_threshold_3_data[7:0] p 90 3e lower_threshold_3_cnfg - lower threshold for leaky bucket configuration 3 lower_threshold_3_data[7:0] p 90 3f bucket_size_3_cnfg - bucket size for leaky bucket configuration 3 bucket_size_3_data[7:0] p 90 40 decay_rate_3_cnfg - decay rate for leaky bucket configuration 3 ------ decay_rate_3_data [1:0] p91 table 41: register list and map (continued) address (hex) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reference page
IDT82V3285 wan pl l programming information 59 december 9, 2008 41 in_freq_read_ch_cnfg - input clock frequency read channel selection - - - - in_freq_read_ch[3:0] p 91 42 in_freq_read_sts - input clock frequency read value in_freq_value[7:0] p 92 44 in1_in2_sts - input clock 1 & 2 sta- tus - in2_freq _hard_a larm in2_no_a ctivity_a larm in2_ph_l ock_ala rm - in1_freq _hard_a larm in1_no_a ctivity_a larm in1_ph_l ock_ala rm p93 45 in3_in4_sts - input clock 3 & 4 sta- tus - in4_freq _hard_a larm in4_no_a ctivity_a larm in4_ph_l ock_ala rm - in3_freq _hard_a larm in3_no_a ctivity_a larm in3_ph_l ock_ala rm p94 48 in5_sts - input clock 5 status - - - - - in5_freq _hard_a larm in5_no_a ctivity_a larm in5_ph_l ock_ala rm p95 t0 / t4 dpll input clock selection registers 4a input_valid1_sts - input clocks validity 1 - - in[4:1] - - p 96 4b input_valid2_sts - input clocks validity 2 -----in5--p96 4c remote_input_valid1_cnfg - input clocks validity configuration 1 -d - in4_valid in3_valid in2_valid in1_valid - - p 96 4d remote_input_valid2_cnfg - input clocks validity configuration 2 -----in5_valid--p97 4e priority_table1_sts - priority status 1 * highest_priority_validated[3:0] currently_selected_input[3:0] p 97 4f priority_table2_sts - priority status 2 * third_highest_priority_validated[3:0] second_highest_priority_validated[3:0 ] p98 50 t0_input_sel_cnfg - t0 selected input clock configuration - - - - t0_input_sel[3:0] p 99 51 t4_input_sel_cnfg - t4 selected input clock configuration - t4_lock_ t0 t0_for_t 4 t4_test_ t0_ph t4_input_sel[3:0] p 100 t0 / t4 dpll state machine control registers 52 operating_sts - dpll operating status ex_sync _alarm_ mon t4_dpll_ lock t0_dpll_ soft_fre q_alarm t4_dpll_ soft_fre q_alram t0_dpll_ lock t0_dpll_operating_mode[2:0] p 101 53 t0_operating_mode_cnfg - t0 dpll operating mode configuration - - - - - t0_operating_mode[2:0] p 102 54 t4_operating_mode_cnfg - t4 dpll operating mode configuration - - - - - t4_operating_mode[2:0] p 102 t0 / t4 dpll & apll c onfiguration registers 55 t0_dpll_apll_path_cnfg - t0 dpll & apll path configuration t0_apll_path[3:0] t0_gsm_obsai_16e1 _16t1_sel[1:0] t0_12e1_24t1_e3_t3 _sel[1:0] p103 56 t0_dpll_start_bw_damping_c nfg - t0 dpll start bandwidth & damping factor configuration t0_dpll_start_damping[2:0] t0_dpll_start_bw[4:0] p 104 57 t0_dpll_acq_bw_damping_cnf g - t0 dpll acquisition bandwidth & damping factor configuration t0_dpll_acq_damping[2:0] t0_dpll_acq_bw[4:0] p 105 table 41: register list and map (continued) address (hex) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reference page
IDT82V3285 wan pl l programming information 60 december 9, 2008 58 t0_dpll_locked_bw_damping_ cnfg - t0 dpll locked bandwidth & damping factor configuration t0_dpll_locked_damping[2:0 ] t0_dpll_locked_bw[4:0] p 106 59 t0_bw_overshoot_cnfg - t0 dpll bandwidth overshoot configu- ration auto_bw _sel - - - t0_limt - - - p 107 5a phase_loss_coarse_limit_cnf g - phase loss coarse detector limit configuration * coarse_ ph_los_l imt_en wide_en multi_ph _app multi_ph _8k_4k_2 k_en ph_los_coarse_limt[3:0] p 108 5b phase_loss_fine_l imit_cnfg - phase loss fine detector limit con- figuration * fine_ph_ los_limt _en fast_los _sw - - - ph_los_fine_limt[2:0] p 109 5c t0_holdover_mode_cnfg - t0 dpll holdover mode configuration man_hol dover auto_av g fast_avg read_av g temp_holdover_m ode[1:0] --p110 5d t0_holdover_freq[7:0]_cnfg - t0 dpll holdover frequency config- uration 1 t0_holdover_freq[7:0] p 110 5e t0_holdover_freq[15:8]_cnfg - t0 dpll holdover frequency con- figuration 2 t0_holdover_freq[15:8] p 111 5f t0_holdover_freq[23:16]_cnfg - t0 dpll holdover frequency con- figuration 3 t0_holdover_freq[23:16] p 111 60 t4_dpll_apll_path_cnfg - t4 dpll & apll path configuration t4_apll_path[3:0] t4_gsm_gps_16e1_1 6t1_sel[1:0] t4_12e1_24t1_e3_t3 _sel[1:0] p112 61 t4_dpll_locked_bw_damping_ cnfg - t4 dpll locked bandwidth & damping factor configuration t4_dpll_locked_d amping[2:0] - - - t4_dpll_locked_b w[1:0] p113 62 current_dpll_freq[7:0]_sts - dpll current frequency status 1 * current_dpll_freq[7:0] p 113 63 current_dpll_freq[15:8]_sts - dpll current frequency status 2 * current_dpll_freq[15:8] p 113 64 current_dpll_freq[23:16]_sts - dpll current frequency status 3 * current_dpll_freq[23:16] p 114 65 dpll_freq_soft_limit_cnfg - dpll soft limit configuration freq_lim t_ph_los dpll_freq_soft_limt[6:0] p 114 66 dpll_freq_hard_limit[7:0]_cnf g - dpll hard limit configuration 1 dpll_freq_hard_limt[7:0] p 114 67 dpll_freq_hard_limit[15:8]_cn fg - dpll hard limit configuration 2 dpll_freq_hard_limt[15:8] p 115 68 current_dpll_phase[7:0]_sts - dpll current phase status 1 * current_ph_data[7:0] p 115 69 current_dpll_phase[15:8]_sts - dpll current phase status 2 * current_ph_data[15:8] p 115 6a t0_t4_apll_bw_cnfg - t0 / t4 apll bandwidth configuration - - t0_apll_bw[1:0] - - t4_apll_bw[1:0] p 116 output configuration registers 6d out1_freq_cnfg - output clock 1 frequency configuration out1_path_sel[3:0] out1_divider[3:0] p 117 table 41: register list and map (continued) address (hex) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reference page
IDT82V3285 wan pl l programming information 61 december 9, 2008 7.2 register description 7.2.1 global control registers id[7:0] - device id 1 6e out2_freq_cnfg - output clock 2 frequency configuration out2_path_sel[3:0] out2_divider[3:0] p 118 6f out3_freq_cnfg - output clock 3 frequency configuration out3_path_sel[3:0] out3_divider[3:0] p 119 70 out4_freq_cnfg - output clock 4 frequency configuration out4_path_sel[3:0] out4_divider[3:0] p 120 71 out5_freq_cnfg - output clock 5 frequency configuration out5_path_sel[3:0] out5_divider[3:0] p 121 72 output_inv2 - output clock 4 & 5 invert configuration - out5_inv out4_inv p 121 73 output_inv1 - output clock 1 ~ 3 invert configuration - out3_inv out2_inv out1_inv - p 122 74 fr_mfr_sync_cnfg - frame sync & multiframe sync output configura- tion in_2k_4k_ 8k_inv 8k_en 2k_en 2k_8k_pu l_positi on 8k_inv 8k_pul 2k_inv 2k_pul p 123 pbo & phase offset control registers 78 phase_mon_pbo_cnfg - phase transient monitor & pbo configura- tion in_noise _window - ph_mon_ en ph_mon_ pbo_en ph_tr_mon_limt[3:0] p 124 7a phase_offset[7:0]_cnfg - phase offset configuration 1 ph_offset[7:0] p 124 7b phase_offset[9:8]_cnfg - phase offset configuration 2 ph_offs et_en -----ph_offset[9:8]p125 synchronization configuration registers 7c sync_monitor_cnfg - sync mon- itor configuration - sync_mon_limt[2:0] - - - - p 126 7d sync_phase_cnfg - sync phase configuration ------sync_ph1[1:0]p126 table 41: register list and map (continued) address (hex) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reference page address: 00h type: read default value: 10001000 bit name description 7 - 0 id[7:0] refer to the description of the id[15:8] bits (b7~0, 01h). 76543210 id7 id6 id5 id4 id3 id2 id1 id0
IDT82V3285 wan pl l programming information 62 december 9, 2008 id[15:8] - device id 2 mpu_pin_sts - mpu_mode[2:0] pins status nominal_freq[7:0]_cnfg - crystal oscillator frequency offset calibration configuration 1 nominal_freq[15:8]_cnfg - crystal oscillator frequency offset calibration configuration 2 address: 01h type: read default value: 00010001 bit name description 7 - 0 id[15:8] the value in the id[15:0] bits are pre-set, representing the identification number for the IDT82V3285. address: 02h type: read default value: xxxxxxxx bit name description 7 - 3 - reserved. 2 - 0 mpu_pin_sts[2:0] these bits indicate the value of the mpu_mode[2:0] pins. the default value of these bits is determined by the mpu_mode[2:0] pins during reset. address: 04h type: read / write default value: 00000000 bit name description 7 - 0 nominal_freq_value[7:0] refer to the description of the nominal_freq_value[23:16] bits (b7~0, 06h). address: 05h type: read / write default value: 00000000 bit name description 7 - 0 nominal_freq_value[15:8] refer to the description of the nominal_freq_value[23:16] bits (b7~0, 06h). 76543210 id15 id14 id13 id12 id11 id10 id9 id8 76543 2 1 0 - - - - - mpu_pin_sts2 mpu_pin_sts1 mpu_pin_sts0 76543210 nominal_fre q_value7 nominal_fre q_value6 nominal_fre q_value5 nominal_fre q_value4 nominal_fre q_value3 nominal_fre q_value2 nominal_fre q_value1 nominal_fre q_value0 76543210 nominal_fre q_value15 nominal_fre q_value14 nominal_fre q_value13 nominal_fre q_value12 nominal_fre q_value11 nominal_fre q_value10 nominal_fre q_value9 nominal_fre q_value8
IDT82V3285 wan pl l programming information 63 december 9, 2008 nominal_freq[23:16]_cnfg - crystal oscillator fr equency offset calibra tion configuration 3 t4_t0_reg_sel_cnfg - t0 / t4 re gisters selection configuration address: 06h type: read / write default value: 00000000 bit name description 7 - 0 nominal_freq_value[23:16] the nominal_freq_value[23:0] bits represent a 2?s complement signed integer. if the value is multiplied by 0.0000884, the calibration value for the master clock in ppm will be gotten. for example, the frequency offset on osci is +3 ppm. though -3 ppm should be compensated, the calibration value is calculated as +3 ppm: 3 0.0000884 = 33937 (dec.) = 8490 (hex); so ?008490? should be written into these bits. the calibration range is within 741 ppm. address: 07h type: read / write default value: xxx0xxxx bit name description 7 - 5 - reserved. 4 t4_t0_sel a part of the registers are shared by t0 and t4 paths. these registers are addressed 27h, 28h, 2bh, 4eh, 4fh, 5ah, 5bh, 62h ~ 64h, 68h and 69h. this bit determines whether the register configuration is available for t0 or t4 path. 0: t0 path (default). 1: t4 path. 3 - 0 - reserved. 76543210 nominal_fre q_value23 nominal_fre q_value22 nominal_fre q_value21 nominal_fre q_value20 nominal_fre q_value19 nominal_fre q_value18 nominal_fre q_value17 nominal_fre q_value16 76543210 - - - t4_t0_sel - - - -
IDT82V3285 wan pl l programming information 64 december 9, 2008 phase_alarm_time_out_cnfg - phase lo ck alarm time-out configuration address: 08h type: read / write default value: 00110010 bit name description 7 - 6 multi_factor[1:0] these bits determine a factor which has a relationship with a period in seconds. a phase lock alarm will be raised if the t0 selected input clock is not locked in t0 dpll within this period. if the ph_alarm_timeout bit (b5, 09h) is ?1?, the phase lock alarm will be cleared after this period (starting from when the alarm is raised). refer to the description of the time_out_value[5:0] bits (b5~0, 08h). 00: 2 (default) 01: 4 10: 8 11: 16 5 - 0 time_out_value[5:0] these bits represent an unsigned integer. if the value in these bits is multiplied by the value in the multi_factor[1:0] bits (b7~6, 08h), a period in seconds will be gotten. a phase lock alarm will be raised if the t0 selected input clock is not locked in t0 dpll within this period. if the ph_alarm_timeout bit (b5, 09h) is ?1?, the phase lock alarm will be cleared after this period (starting from when the alarm is raised). 76543 2 1 0 multi_facto r1 multi_facto r0 time_out_va lue5 time_out_va lue4 time_out_va lue3 time_out_va lue2 time_out_va lue1 time_out_val ue0
IDT82V3285 wan pl l programming information 65 december 9, 2008 input_mode_cnfg - inpu t mode configuration address: 09h type: read / write default value: 10100xx0 bit name description 7 auto_ext_sync_en refer to the description of the ext_sync_en bit (b6, 09h). 6 ext_sync_en this bit, together with the auto_ext_sync_en bit (b7, 09h ), determines whether ex_sync1 is enabled to synchronize the frame sync output signals. 5 ph_alarm_timeout this bit determines how to clear the phase lock alarm. 0: the phase lock alarm will be cleared when a ?1? is wr itten to the corresponding inn_ph_lock_alarm bit (b4/0, 44h & 45h & 48h). 1: the phase lock alarm will be cleared after a period ( = time_out_value[5:0] (b5~0, 08h) x multi_factor[1:0] (b7~6, 08h) in seconds ) which starts from when the alarm is raised. (default) 4 - 3 sync_freq[1:0] these bits set the frequency of the frame sync signal input on the ex_sync1 pin. 00: 8 khz (default) 01: 8 khz. 10: 4 khz. 11: 2 khz. 2 in_sonet_sdh this bit selects the sdh or sonet network type. 0: sdh. the dpll required clock is 2.048 mhz when the in_fre q[3:0] bits (b3~0, 16h & 17h & 19h) are ?0001?; the t0/t4 dpll output from the 16e1/16t1 path is 16e1. 1: sonet. the dpll required clock is 1.544 mhz when the in_freq[3:0] bits (b3~0, 16h & 17h & 19h) are ?0001?; the t0/ t4 dpll output from the 16e1/16t1 path is 16t1. the default value of this bit is determined by the sonet/ sdh pin during reset. 1 master_slave this bit is read only. it indicates the value of the ms/ sl pin. its default value is determined by the ms/ sl pin during reset. 0 revertive_mode this bit selects revertive or non-revertive switch for t0 path. 0: non-revertive switch. (default) 1: revertive switch. 76543210 auto_ext_sy nc_en ext_sync_en ph_alarm_ti meout sync_freq1 sync_freq0 in_sonet_sd h master_slav e revertive_m ode auto_ext_sync_en ext_syn c_en synchronization don?t-care 0 disabled (default) 01 enabled 1 1 enabled if the t0 selected input clock is in5; otherwise, disabled.
IDT82V3285 wan pl l programming information 66 december 9, 2008 differential_in_out_osci_cnfg - di fferential input / output port & master clock configuration address: 0ah type: read / write default value: xxxxx001 bit name description 7 - 3 - reserved. 2osc_edge this bit selects a better active edge of the master clock. 0: the rising edge. (default) 1: the falling edge. 1 out5_pecl_lvds this bit selects a port technology for out5. 0: lvds. (default) 1: pecl. 0 out4_pecl_lvds this bit selects a port technology for out4. 0: lvds. 1: pecl. (default) 7654 3 2 1 0 ---- -osc_edgeout5_pecl_lvdsout4_pecl_lvds
IDT82V3285 wan pl l programming information 67 december 9, 2008 mon_sw_pbo_cnfg - frequency monitor, input clock select ion & pbo control address: 0bh type: read / write default value: 100x01x1 bit name description 7 freq_mon_clk the bit selects a reference clock for input clock frequency monitoring. 0: the output of t0 dpll. 1: the master clock. (default) 6 los_flag_to_tdo the bit determines whether the interrupt of t0 selected input clock fail - is reported by the tdo pin. 0: not reported. tdo pin is used as jtag test data output which complies with ieee 1149.1. (default) 1: reported. tdo pin mimics the state of the t0_main_ref_fail ed bit (b6, 0eh) and does not strictly comply with ieee 1149.1. 5 ultr_fast_sw this bit determines whether the t0 selected input clock is valid when missing 2 consecutive clock cycles or more. 0: valid. (default) 1: invalid. 4ext_sw this bit determines the t0 input clock selection. 0: forced selection or automatic selection, as controlled by the t0_input_sel[3:0] bits (b3~0, 50h). 1: external fast selection. the default value of this bit is determined by the ff_srcsw pin during reset. 3 pbo_frez this bit is valid only when the pbo is enabled by the pbo_en bit (b2, 0bh). it determines whether pbo is frozen at the cur- rent phase offset when a pbo event is triggered. 0: not frozen. (default) 1: frozen. further pbo events are ignored and the current phase offset is maintained. 2 pbo_en this bit determines whether pbo is enabled when the t0 selected input clock switch or the t0 dpll exiting from holdover mode or free-run mode occurs. 0: disabled. 1: enabled. (default) 1-reserved. 0 freq_mon_hard_en this bit determines whether the frequency hard alarm is enabled when the frequency of the input clock with respect to the reference clock is above the frequency hard alarm threshold. the reference clock can be the output of t0 dpll or the mas- ter clock, as determined by the freq_mon_clk bit (b7, 0bh). 0: disabled. 1: enabled. (default) 76 5 43210 freq_mon_c lk los_flag_to _tdo ultr_fast_sw ext_sw pbo_frez pbo_en - freq_mon_h ard_en
IDT82V3285 wan pl l programming information 68 december 9, 2008 ms_sl_ctrl_cnfg - master slave control protection_cnfg - register pr otection mode configuration address: 13h type: read / write default value: xxxxxxx0 bit name description 7 - 1 - reserved. 0 ms_sl_ctrl this bit, together with the ms/ sl pin, controls whether the device is configured as the master or as the slave. the default value of this bit is ?0?. address: 7eh type: read / write default value: 10000101 bit name description 7 - 0 protection_data[7:0] these bits select a register write protection mode. 00000000 - 10000100, 10000111 - 1 1111111: protected mode. no other registers can be written except this register. 10000101: fully unprotected mode. all the writable registers can be written. (default) 10000110: single unprotected mode. one more register can be written besides this register. after write operation (not including writing a ?1? to clear the bit to ?0?), the device automatically switches to protected mode. 7 6543210 - ------ms_sl_ctrl master/slave control result ms/ sl pin ms_sl_ctrl bit high 0master 1slave low 0slave 1master 76543210 protection_ data7 protection_ data6 protection_ data5 protection_ data4 protection_ data3 protection_ data2 protection_ data1 protection_ data0
IDT82V3285 wan pl l programming information 69 december 9, 2008 mpu_sel_cnfg - microprocessor in terface mode configuration address: 7fh type: read / write default value: xxxxxxxx bit name description 7 - 3 - reserved. 2 - 0 mpu_sel_cnfg[2:0] these bits select a microprocessor interface mode: 000: reserved. 001: erpom mode. 010: multiplexed mode. 011: intel mode. 100: motorola mode. 101: serial mode. 110, 111: reserved. the default value of these bits are determined by the mpu_mode[2:0] pins during reset. 76543 2 1 0 - - - - - mpu_sel_cnfg2 mpu_sel_cnfg1 mpu_sel_cnfg0
IDT82V3285 wan pl l programming information 70 december 9, 2008 7.2.2 interrupt registers interrupt_cnfg - interrupt configuration interrupts1_sts - interrupt status 1 address: 0ch type: read / write default value: xxxxxx10 bit name description 7 - 2 - reserved. 1hz_en this bit determines the output characteristics of the int_req pin. 0: the output on the int_req pin is high/low when the interrupt is active; the output is the opposite when the interrupt is ina ctive. 1: the output on the int_req pin is high/low when the interrupt is active; the output is in high impedance state when the inter rupt is inactive. (default) 0int_pol this bit determines the active level on the int_req pin for an active interrupt indication. 0: active low. (default) 1: active high. address: 0dh type: read / write default value: 11111111 bit name description 7 - 6 - reserved. 5 - 2 inn this bit indicates the validity changes (from ?valid? to ?invalid? or from ?invalid? to ?valid?) for the corresponding inn; i.e ., whether there is a transition (from ?0? to ?1? or from ?1? to ?0?) on the corresponding inn bit (b5~2, 4ah). here n is any one of 4 to 1. 0: has not changed. 1: has changed. (default) this bit is cleared by writing a ?1?. 1 - 0 - reserved. 76543210 ------hz_enint_pol 76543210 - - in4 in3 in2 in1 - -
IDT82V3285 wan pl l programming information 71 december 9, 2008 interrupts2_sts - interrupt status 2 address: 0eh type: read / write default value: 00111111 bit name description 7 t0_operating_mode this bit indicates the operating mode switch for t0 dpll; i.e., whether the value in the t0_dpll_operating_mode[2:0] bits (b2~0, 52h) changes. 0: has not switched. (default) 1: has switched. this bit is cleared by writing a ?1?. 6 t0_main_ref_failed this bit indicates whether the t0 selected input clock has failed. the t0 selected input clock fails when its validity changes from ?valid? to ?invalid?; i.e., when there is a transition from ?1? to ?0? on the corresponding inn bit (4ah, 4bh). 0: has not failed. (default) 1: has failed. this bit is cleared by writing a ?1?. 5 - 3 - reserved. 2in5 this bit indicates the validity changes (from ?valid? to ?invalid? or from ?invalid? to ?valid?) for in5 for t0 path, i.e., whe ther there is a transition (from ?0? to ?1? or from ?1? to ?0?) on in5 bit (b2, 4bh). 0: has not changed. 1: has changed. (default) this bit is cleared by writing a ?1?. 1 - 0 - reserved. 7 6 543210 t0_operating _mode t0_main_ref_f ailed ---in5--
IDT82V3285 wan pl l programming information 72 december 9, 2008 interrupts3_sts - interrupt status 3 interrupts1_enable_cnfg - interrupt control 1 address: 0fh type: read / write default value: 11x10000 bit name description 7 ex_sync_alarm this bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from ?0? to ?1? on the ex_sync_alarm_mon bit (b7, 52h). 0: not raised. 1: raised. (default) this bit is cleared by writing a ?1?. 6t4_sts this bit indicates the t4 dpll locking status changes (from ?locked? to ?unlocked? or from ?unlocked? to ?locked?); i.e., wheth er there is a transition (from ?0? to ?1? or from ?1? to ?0?) on the t4_dpll_lock bit (b6, 52h). 0: has not changed. 1: has changed. (default) this bit is cleared by writing a ?1?. 5 - reserved. 4input_to_t4 this bit indicates whether all the input clocks for t4 path change to be unqualified; i.e., whether the highest_priority_validated[3:0] bits (b7~4, 4eh) are se t to ?0000? when these bits are available for t4 path. 0: has not changed. 1: has changed. (default) this bit is cleared by writing a ?1?. 3 - 0 - reserved. address: 10h type: read / write default value: 00000000 bit name description 7 - 6 - reserved. 5 - 2 inn this bit controls whether the interrupt is enabled to be reported on the int_req pin when the input clock validity changes (fro m ?valid? to ?invalid? or from ?invalid? to ?valid?), i.e., when the corresponding inn bit (b5~2, 0dh) is ?1?. here n is any one of 4 to 1. 0: disabled. (default) 1: enabled. 0 -1 - reserved 7 6543210 ex_sync_alarm t4_sts - input_to_t4 - - - - 76543210 - - in4 in3 in2 in1 - -
IDT82V3285 wan pl l programming information 73 december 9, 2008 interrupts2_enable_cnfg - interrupt control 2 interrupts3_enable_cnfg - interrupt control 3 address: 11h type: read / write default value: 00000000 bit name description 7 t0_operating_mode this bit controls whether the interrupt is enabled to be reported on the int_req pin when the t0 dpll operating mode switches, i.e., when the t0_operating_mode bit (b7, 0eh) is ?1?. 0: disabled. (default) 1: enabled. 6 t0_main_ref_failed this bit controls whether the interrupt is enabled to be reported on the int_req pin when the t0 selected input clock has failed; i.e., when the t0_main_ref_failed bit (b6, 0eh) is ?1?. 0: disabled. (default) 1: enabled. 5 - 3 - reserved. 2in5 this bit controls whether the interrupt is enabled to be reported on the int_req pin when the input clock validity changes (from ?valid? to ?invalid? or from ?invalid? to ?valid?), i.e., when in5 bit (b2, 0eh) is ?1?. 0: disabled. (default) 1: enabled. 1 - 0 - reserved. address: 12h type: read / write default value: 00x00000 bit name description 7 ex_sync_alarm this bit controls whether the interrupt is enabled to be reported on the int_req pin when an external sync alarm has occurred, i.e., when the ex_sync_alarm bit (b7, 0fh) is ?1?. 0: disabled. (default) 1: enabled. 6t4_sts this bit controls whether the interrupt is enabled to be reported on the int_req pin when the t4 dpll locking status changes (from ?locked? to ?unlocked? or from ?unlocked? to ?locked?), i.e., when the t4_sts bit (b6, 0fh) is ?1?. 0: disabled. (default) 1: enabled. 5-reserved. 4 input_to_t4 this bit controls whether the interrupt is enabled to be reported on the int_req pin when all the input clocks for t4 path become unqualified, i.e., when the input_to_t4 bit (b4, 0fh) is ?1?. 0: disabled. (default) 1: enabled. 3 - 0 - reserved. 7 6 543210 t0_operating _mode t0_main_ref_f ailed ---in5-- 7 6543210 ex_sync_alarm t4_sts - input_to_t4 - - - -
IDT82V3285 wan pl l programming information 74 december 9, 2008 7.2.3 input clock frequency & priority configuration registers in1_cnfg - input cloc k 1 configuration address: 16h type: read / write default value: 00000000 bit name description 7 direct_div refer to the descript ion of the lock_8k bit (b6, 16h). 6lock_8k this bit, together with the direct_div bit (b7, 16h), determine s whether the divn divider or the lock 8k divider is used for in1: 5 - 4 bucket_sel[1:0] these bits select one of the four groups of leaky bucket configuration registers for in1: 00: group 0; the addresses of the configuration registers are 31h ~ 34h. (default) 01: group 1; the addresses of the configuration registers are 35h ~ 38h. 10: group 2; the addresses of the configuration registers are 39h ~ 3ch. 11: group 3; the addresses of the configuration registers are 3dh ~ 40h. 3 - 0 in_freq[3:0] these bits set the dpll required frequency for in1: 0000: 8 khz. (default) 0001: 1.544 mhz (when the in_sonet_sdh bit (b2, 09h) is ?1?) / 2.048 mhz (when the in_sonet _sdh bit (b2, 09h) is ?0?). 0010: 6.48 mhz. 0011: 19.44 mhz. 0100: 25.92 mhz. 0101: 38.88 mhz. 0110 ~ 1000: reserved. 1001: 2 khz. 1010: 4 khz. 1011 ~ 1111: reserved. for in1, the required frequency should not be set higher than that of the input clock. 76543210 direct_div lock_8k bucket_sel1 bucket_sel 0 in_freq3 in_freq2 in_freq1 in_freq0 direct_div bit lock_8k bit used divider 0 0 both bypassed (default) 0 1 lock 8k divider 10 divn divider 11 reserved
IDT82V3285 wan pl l programming information 75 december 9, 2008 in2_cnfg - input cloc k 2 configuration address: 17h type: read / write default value: 00000000 bit name description 7 direct_div refer to the descript ion of the lock_8k bit (b6, 17h). 6lock_8k this bit, together with the direct_div bit (b7, 17h), determines whether the divn divider or the lock 8k divider is used for in2: 5 - 4 bucket_sel[1:0] these bits select one of the four groups of leaky bucket configuration registers for in2: 00: group 0; the addresses of the configuration registers are 31h ~ 34h. (default) 01: group 1; the addresses of the configuration registers are 35h ~ 38h. 10: group 2; the addresses of the configuration registers are 39h ~ 3ch. 11: group 3; the addresses of the configuration registers are 3dh ~ 40h. 3 - 0 in_freq[3:0] these bits set the dpll required frequency for in2 0000: 8 khz. (default) 0001: 1.544 mhz (when the in_sonet_sdh bit (b2, 09h) is ?1?) / 2.048 mhz (when the in_sonet _sdh bit (b2, 09h) is ?0?). 0010: 6.48 mhz. 0011: 19.44 mhz. 0100: 25.92 mhz. 0101: 38.88 mhz. 0110 ~ 1000: reserved. 1001: 2 khz. 1010: 4 khz. 1011 ~ 1111: reserved. for the in2, the required frequency should not be set higher than that of the input clock. 76543210 direct_div lock_8k bucket_sel1 bucket_sel 0 in_freq3 in_freq2 in_freq1 in_freq0 direct_div bit lock_8k bit used divider 0 0 both bypassed (default) 0 1 lock 8k divider 10 divn divider 11 reserved
IDT82V3285 wan pl l programming information 76 december 9, 2008 in3_in4_hf_div_cnfg - input clock 3 & 4 high frequency divider configuration address: 18h type: read / write default value: 00xxxx00 bit name description 7 - 6 in4_div[1:0] these bits determine whether the hf divider is used and what the division factor is for in4 frequency division: 00: bypassed. (default) 01: divided by 4. 10: divided by 5. 11: reserved. 5 - 2 - reserved. 1 - 0 in3_div[1:0] these bits determine whether the hf divider is used and what the division factor is for in3 frequency division: 00: bypassed. (default) 01: divided by 4. 10: divided by 5. 11: reserved. 76543210 in4_div1 in4_div0 - - - - in3_div1 in3_div0
IDT82V3285 wan pl l programming information 77 december 9, 2008 in3_cnfg - input cloc k 3 configuration address: 19h type: read / write default value: 00000011 bit name description 7 direct_div refer to the descript ion of the lock_8k bit (b6, 19h). 6lock_8k this bit, together with the direct_div bit (b7, 19h), determines whether the divn divider or the lock 8k divider is used for in3: 5 - 4 bucket_sel[1:0] these bits select one of the four groups of leaky bucket configuration registers for in3: 00: group 0; the addresses of the configuration registers are 31h ~ 34h. (default) 01: group 1; the addresses of the configuration registers are 35h ~ 38h. 10: group 2; the addresses of the configuration registers are 39h ~ 3ch. 11: group 3; the addresses of the configuration registers are 3dh ~ 40h. 3 - 0 in_freq[3:0] these bits set the dpll required frequency for in3: 0000: 8 khz. 0001: 1.544 mhz (when the in_sonet_sdh bit (b2, 09h) is ?1?) / 2.048 mhz (when the in_sonet _sdh bit (b2, 09h) is ?0?). 0010: 6.48 mhz. 0011: 19.44 mhz. (default) 0100: 25.92 mhz. 0101: 38.88 mhz. 0110 ~ 1000: reserved. 1001: 2 khz. 1010: 4 khz. 1011 ~ 1111: reserved. the required frequency should not be set higher than that of the input clock. 76543210 direct_div lock_8k bucket_sel1 bucket_sel 0 in_freq3 in_freq2 in_freq1 in_freq0 direct_div bit lock_8k bit used divider 0 0 both bypassed (default) 0 1 lock 8k divider 10 divn divider 11 reserved
IDT82V3285 wan pl l programming information 78 december 9, 2008 in4_cnfg - input cloc k 4 configuration address: 1ah type: read / write default value: 00000011 bit name description 7 direct_div refer to the descriptio n of the lock_8k bit (b6, 1ah). 6lock_8k this bit, together with the direct_div bit (b7, 1ah), determine s whether the divn divider or the lock 8k divider is used for in4: 5 - 4 bucket_sel[1:0] these bits select one of the four groups of leaky bucket configuration registers for in4 00: group 0; the addresses of the configuration registers are 31h ~ 34h. (default) 01: group 1; the addresses of the configuration registers are 35h ~ 38h. 10: group 2; the addresses of the configuration registers are 39h ~ 3ch. 11: group 3; the addresses of the configuration registers are 3dh ~ 40h. 3 - 0 in_freq[3:0] these bits set the dpll required frequency for in4: 0000: 8 khz. 0001: 1.544 mhz (when the in_sonet_sdh bit (b2, 09h) is ?1?) / 2.048 mhz (when the in_sonet _sdh bit (b2, 09h) is ?0?). 0010: 6.48 mhz. 0011: 19.44 mhz. (default) 0100: 25.92 mhz. 0101: 38.88 mhz. 0110 ~ 1000: reserved. 1001: 2 khz. 1010: 4 khz. 1011 ~ 1111: reserved. for in4, the required frequency should not be set higher than that of the input clock. 76543210 direct_div lock_8k bucket_sel1 bucket_sel 0 in_freq3 in_freq2 in_freq1 in_freq0 direct_div bit lock_8k bit used divider 0 0 both bypassed (default) 0 1 lock 8k divider 10 divn divider 11 reserved
IDT82V3285 wan pl l programming information 79 december 9, 2008 in5_cnfg - input cloc k 5 configuration address: 1fh type: read / write default value: 0000xxxx bit name description 7 direct_div refer to the descriptio n of the lock_8k bit (b6, 1fh). 6lock_8k this bit, together with the direct_div bit (b7, 1fh), determine s whether the divn divider or the lock 8k divider is used for in5: 5 - 4 bucket_sel[1:0] these bits select one of the four groups of leaky bucket configuration registers for in5: 00: group 0; the addresses of the configuration registers are 31h ~ 34h. (default) 01: group 1; the addresses of the configuration registers are 35h ~ 38h. 10: group 2; the addresses of the configuration registers are 39h ~ 3ch. 11: group 3; the addresses of the configuration registers are 3dh ~ 40h. 3 - 0 in_freq[3:0] these bits set the dpll required frequency for in5: 0000: 8 khz. 0001: 1.544 mhz (when the in_sonet_sdh bit (b2, 09h) is ?1?) / 2.048 mhz (when the in_sonet _sdh bit (b2, 09h) is ?0?). 0010: 6.48 mhz. 0011: 19.44 mhz. 0100: 25.92 mhz. 0101: 38.88 mhz. 0110 ~ 1000: reserved. 1001: 2 khz. 1010: 4 khz. 1011 ~ 1111: reserved. for in5, the required frequency should not be set higher than that of the input clock. the default value of these bits depends on the device application as follows: in master / slave application, when the device is configured as the master, the default value is ?0001?; when the device is con - figured as the slave, the default value is ?0010?. 76543210 direct_div lock_8k bucket_sel1 bucket_sel 0 in_freq3 in_freq2 in_freq1 in_freq0 direct_div bit lock_8k bit used divider 0 0 both bypassed (default) 0 1 lock 8k divider 10 divn divider 11 reserved
IDT82V3285 wan pl l programming information 80 december 9, 2008 pre_div_ch_cnfg - divn divider channel selection pre_divn[7:0]_cnfg - divn divider division factor configuration 1 address: 23h type: read / write default value: xxxx0000 bit name description 7 - 4 - reserved. 3 - 0 pre_div_ch_value[3:0] this register is an indirect address register for register 24h and 25h. these bits select an input clock. the value set in the pre_divn_value[14:0] bits (25h, 24h) is available for the selected input clock. 0000: reserved. (default) 0001, 0010: reserved. 0011: in1. 0100: in2. 0101: in3 0110: in4 0111, 1000, 1001, 1010: reserved 1011: in5 1100, 1101, 1110, 1111: reserved. address: 24h type: read / write default value: 00000000 bit name description 7 - 0 pre_divn_value[7:0] refer to the description of the pre_divn_value[14:8] bits (b6~0, 25h). 7654 3 2 1 0 - - - - pre_div_ch_value3 pre _div_ch_value2 pr e_div_ch_value1 pre_div_ch_value0 76543210 pre_divn_va lue7 pre_divn_va lue6 pre_divn_va lue5 pre_divn_va lue4 pre_divn_va lue3 pre_divn_va lue2 pre_divn_va lue1 pre_divn_va lue0
IDT82V3285 wan pl l programming information 81 december 9, 2008 pre_divn[14:8]_cnfg - divn divider division factor configuration 2 address: 25h type: read / write default value: x0000000 bit name description 7-reserved. 6 - 0 pre_divn_value[14:8] the division factor for an input clock is the value in the pre_divn_value[14:0] bits plus 1. the input clock is selected by the pre_div_ch_value [3:0] bits (b3~0, 23h). a value from ?0? to ?4bef? (hex) can be written into, corresponding to a division factor from 1 to 19440. the others are reserved. so the divn divider only supports an input clock whose frequency is lower than ( < ) 155.52 mhz. the division factor setting should observe the following order: 1. write the lower eight bits of the division factor to the pre_divn_value[7:0] bits; 2. write the higher eight bits of the division factor to the pre_divn_value[14:8] bits. 76543210 - pre_divn_val ue14 pre_divn_val ue13 pre_divn_val ue12 pre_divn_val ue11 pre_divn_val ue10 pre_divn_val ue9 pre_divn_val ue8
IDT82V3285 wan pl l programming information 82 december 9, 2008 in1_in2_sel_priority_cnfg - input cl ock 1 & 2 priority configuration * address: 27h type: read / write default value: t0 - 01010100 / t4 - 00000000 bit name description 7 - 4 inn_sel_priority[3:0] these bits set the priority of the corresponding inn. here n is 2. 0000: disable inn for automatic selection. (t4 default) 0001: priority 1. 0010: priority 2. 0011: priority 3. 0100: priority 4. 0101: priority 5. (t0 default) 0110: priority 6. 0111: priority 7. 1000: priority 8. 1001: priority 9. 1010: priority 10. 1011: priority 11. 1100: priority 12. 1101: priority 13. 1110: priority 14. 1111: priority 15. 3 - 0 inn_sel_priority[3:0] these bits set the priority of the corresponding inn. here n is 1. 0000: disable inn for automatic selection. (t4 default) 0001: priority 1. 0010: priority 2. 0011: priority 3. 0100: priority 4. (t0 default) 0101: priority 5. 0110: priority 6. 0111: priority 7. 1000: priority 8. 1001: priority 9. 1010: priority 10. 1011: priority 11. 1100: priority 12. 1101: priority 13. 1110: priority 14. 1111: priority 15. 76543210 in2_sel_prio rity3 in2_sel_prio rity2 in2_sel_prio rity1 in2_sel_prio rity0 in1_sel_prio rity3 in1_sel_prio rity2 in1_sel_prio rity1 in1_sel_prio rity0
IDT82V3285 wan pl l programming information 83 december 9, 2008 in3_in4_sel_priority_cnfg - input cl ock 3 & 4 priority configuration * address: 28h type: read / write default value: t0/t4 - 01110110 bit name description 7 - 4 inn_sel_priority[3:0] these bits set the priority of the corresponding inn. here n is 4. 0000: disable inn for automatic selection. 0001: priority 1. 0010: priority 2. 0011: priority 3. 0100: priority 4. 0101: priority 5. 0110: priority 6. 0111: priority 7. (default) 1000: priority 8. 1001: priority 9. 1010: priority 10. 1011: priority 11. 1100: priority 12. 1101: priority 13. 1110: priority 14. 1111: priority 15. 3 - 0 inn_sel_priority[3:0] these bits set the priority of the corresponding inn. here n is 3. 0000: disable inn for automatic selection. 0001: priority 1. 0010: priority 2. 0011: priority 3. 0100: priority 4. 0101: priority 5. 0110: priority 6. (default) 0111: priority 7. 1000: priority 8. 1001: priority 9. 1010: priority 10. 1011: priority 11. 1100: priority 12. 1101: priority 13. 1110: priority 14. 1111: priority 15. 76543210 in4_sel_prio rity3 in4_sel_prio rity2 in4_sel_prio rity1 in4_sel_prio rity0 in3_sel_prio rity3 in3_sel_prio rity2 in3_sel_prio rity1 in3_sel_prio rity0
IDT82V3285 wan pl l programming information 84 december 9, 2008 in5_sel_priority_cnfg - input cl ock 5 priority configuration * address: 2bh type: read / write default value: 11011100 (t0 master)/11010001 (t0 slave) 00000000 (t4) bit name description 7 - 4 - reserved 3 - 0 inn_sel_priority[3:0] these bits set the priority of the corresponding inn. here n is 5: 0000: disable inn for automatic selection. (t4 default) 0001: priority 1. (t0 slave default) 0010: priority 2. 0011: priority 3. 0100: priority 4. 0101: priority 5. 0110: priority 6. 0111: priority 7. 1000: priority 8. 1001: priority 9. 1010: priority 10. 1011: priority 11. 1100: priority 12. (t0 master default) 1101: priority 13. 1110: priority 14. 1111: priority 15. 76543210 ---- in5_sel_prio rity3 in5_sel_prio rity2 in5_sel_prio rity1 in5_sel_prio rity0
IDT82V3285 wan pl l programming information 85 december 9, 2008 7.2.4 input clock quality monitoring configuration & status registers freq_mon_factor_cnfg - factor of frequency monitor configuration all_freq_mon_threshold_cnfg - fr equency monitor threshold for all input clocks configuration address: 2eh type: read / write default value: xxxx1011 bit name description 7 - 4 - reserved. 3 - 0 freq_mon_factor[3:0] these bits determine a factor. the factor has a relationship with the frequency hard alarm threshold in ppm (refer to the description of the all_freq_hard_threshold[3:0] bi ts (b3~0, 2fh)) and with the frequency of the input clock with respect to the master clock in ppm (refer to the description of the in_freq_value[7:0] bits (b7~0, 42h)). the factor represents the accuracy of the frequency monitor and should be set according to the requirements of differ- ent applications. 0000: 0.0032. 0001: 0.0064. 0010: 0.0127. 0011: 0.0257. 0100: 0.0514. 0101: 0.103. 0110: 0.206. 0111: 0.412. 1000: 0.823. 1001: 1.646. 1010: 3.292. 1011: 3.81. (default) 1100 - 1111: 4.6. address: 2fh type: read / write default value: xxxx0011 bit name description 7 - 4 - reserved. 3 - 0 all_freq_hard_threshold[3:0] these bits represent an unsigned integer. the frequency hard alarm threshold in ppm can be calculated as follows: frequency hard alarm threshold (ppm) = (all_freq_hard_threshold[3:0] + 1) x freq_mon_factor[3:0] (b3~0, 2eh) this threshold is symmetrical about zero. 76543210 ---- freq_mon_f actor3 freq_mon_f actor2 freq_mon_f actor1 freq_mon_f actor0 7654 3210 ---- all_freq_hard_ threshold3 all_freq_hard_ threshold2 all_freq_hard_ threshold1 all_freq_hard_ threshold0
IDT82V3285 wan pl l programming information 86 december 9, 2008 upper_threshold_0_cnfg - up per threshold for leaky bucket configuration 0 lower_threshold_0_c nfg - lower threshold for leaky bucket configuration 0 bucket_size_0_cnfg - bucket size for leaky bucket configuration 0 address: 31h type: read / write default value: 00000110 bit name description 7 - 0 upper_threshold_0_data[7:0] these bits set an upper threshold for the internal leaky bucket accumulator. when the number of the accumu- lated events is above this threshold, a no-activity alarm is raised. address: 32h type: read / write default value: 00000100 bit name description 7 - 0 lower_threshold_0_data[7:0] these bits set a lower threshold for the internal leaky bucket accumulator. when the number of the accumulated events is below this threshold, the no-activity alarm is cleared. address: 33h type: read / write default value: 00001000 bit name description 7 - 0 bucket_size_0_data[7:0] these bits set a bucket size for the internal leaky bucket accumulator. if the number of the accumulated events reach the bucket size, the accumulator will stop increasing even if further events are detected. 76543210 upper_thre shold_0_dat a7 upper_thre shold_0_dat a6 upper_thre shold_0_dat a5 upper_thre shold_0_dat a4 upper_thre shold_0_dat a3 upper_thre shold_0_dat a2 upper_thre shold_0_dat a1 upper_thre shold_0_dat a0 76543210 lower_thre shold_0_dat a7 lower_thre shold_0_dat a6 lower_thre shold_0_dat a5 lower_thre shold_0_dat a4 lower_thre shold_0_dat a3 lower_thre shold_0_dat a2 lower_thre shold_0_dat a1 lower_thre shold_0_dat a0 76543210 bucket_size _0_data7 bucket_size _0_data6 bucket_size _0_data5 bucket_size _0_data4 bucket_size _0_data3 bucket_size _0_data2 bucket_size _0_data1 bucket_size _0_data0
IDT82V3285 wan pl l programming information 87 december 9, 2008 decay_rate_0_cnfg - decay rate fo r leaky bucket configuration 0 upper_threshold_1_cnfg - up per threshold for leaky bucket configuration 1 lower_threshold_1_c nfg - lower threshold for leaky bucket configuration 1 address: 34h type: read / write default value: xxxxxx01 bit name description 7 - 2 - reserved. 1 - 0 decay_rate_0_data[1:0] these bits set a decay rate for the internal leaky bucket accumulator: 00: the accumulator decreases by 1 in every 128 ms with no event detected. 01: the accumulator decreases by 1 in every 256 ms with no event detected. (default) 10: the accumulator decreases by 1 in every 512 ms with no event detected. 11: the accumulator decreases by 1 in every 1024 ms with no event detected. address: 35h type: read / write default value: 00000110 bit name description 7 - 0 upper_threshold_1_data[7:0] these bits set an upper threshold for the internal leaky bucket accumulator. when the number of the accumu- lated events is above this threshold, a no-activity alarm is raised. address: 36h type: read / write default value: 00000100 bit name description 7 - 0 lower_threshold_1_data[7:0] these bits set a lower threshold for the internal leaky bucket accumulator. when the number of the accumulated events is below this threshold, the no-activity alarm is cleared. 76543210 ------ decay_rate_ 0_data1 decay_rate_ 0_data0 76543210 upper_thre shold_1_dat a7 upper_thre shold_1_dat a6 upper_thre shold_1_dat a5 upper_thre shold_1_dat a4 upper_thre shold_1_dat a3 upper_thre shold_1_dat a2 upper_thre shold_1_dat a1 upper_thre shold_1_dat a0 76543210 lower_thre shold_1_dat a7 lower_thre shold_1_dat a6 lower_thre shold_1_dat a5 lower_thre shold_1_dat a4 lower_thre shold_1_dat a3 lower_thre shold_1_dat a2 lower_thre shold_1_dat a1 lower_thre shold_1_dat a0
IDT82V3285 wan pl l programming information 88 december 9, 2008 bucket_size_1_cnfg - bucket size for leaky bucket configuration 1 decay_rate_1_cnfg - decay rate fo r leaky bucket configuration 1 upper_threshold_2_cnfg - up per threshold for leaky bucket configuration 2 address: 37h type: read / write default value: 00001000 bit name description 7 - 0 bucket_size_1_data[7:0] these bits set a bucket size for the internal leaky bucket accumulator. if the number of the accumulated events reach the bucket size, the accumulator will stop increasing even if further events are detected. address: 38h type: read / write default value: xxxxxx01 bit name description 7 - 2 - reserved. 1 - 0 decay_rate_1_data[1:0] these bits set a decay rate for the internal leaky bucket accumulator: 00: the accumulator decreases by 1 in every 128 ms with no event detected. 01: the accumulator decreases by 1 in every 256 ms with no event detected. (default) 10: the accumulator decreases by 1 in every 512 ms with no event detected. 11: the accumulator decreases by 1 in every 1024 ms with no event detected. address: 39h type: read / write default value: 00000110 bit name description 7 - 0 upper_threshold_2_data[7:0] these bits set an upper threshold for the internal leaky bucket accumulator. when the number of the accumu- lated events is above this threshold, a no-activity alarm is raised. 76543210 bucket_size _1_data7 bucket_size _1_data6 bucket_size _1_data5 bucket_size _1_data4 bucket_size _1_data3 bucket_size _1_data2 bucket_size _1_data1 bucket_size _1_data0 7654321 0 ------ decay_rate_ 1_data1 decay_rate_ 1_data0 76543210 upper_thre shold_2_dat a7 upper_thre shold_2_dat a6 upper_thre shold_2_dat a5 upper_thre shold_2_dat a4 upper_thre shold_2_dat a3 upper_thre shold_2_dat a2 upper_thre shold_2_dat a1 upper_thre shold_2_dat a0
IDT82V3285 wan pl l programming information 89 december 9, 2008 lower_threshold_2_c nfg - lower threshold for leaky bucket configuration 2 bucket_size_2_cnfg - bucket size for leaky bucket configuration 2 decay_rate_2_cnfg - decay rate fo r leaky bucket configuration 2 address: 3ah type: read / write default value: 00000100 bit name description 7 - 0 lower_threshold_2_data[7:0] these bits set a lower threshold for the internal leaky bucket accumulator. when the number of the accumu- lated events is below this threshold, the no-activity alarm is cleared. address: 3bh type: read / write default value: 00001000 bit name description 7 - 0 bucket_size_2_data[7:0] these bits set a bucket size for the internal leaky bucket accumulator. if the number of the accumulated events reaches the bucket size, the accumulator will stop increasing even if further events are detected. address: 3ch type: read / write default value: xxxxxx01 bit name description 7 - 2 - reserved. 1 - 0 decay_rate_2_data[1:0] these bits set a decay rate for the internal leaky bucket accumulator: 00: the accumulator decreases by 1 in every 128 ms with no event detected. 01: the accumulator decreases by 1 in every 256 ms with no event detected. (default) 10: the accumulator decreases by 1 in every 512 ms with no event detected. 11: the accumulator decreases by 1 in every 1024 ms with no event detected. 76543210 lower_thre shold_2_dat a7 lower_thre shold_2_dat a6 lower_thre shold_2_dat a5 lower_thre shold_2_dat a4 lower_thre shold_2_dat a3 lower_thre shold_2_dat a2 lower_thre shold_2_dat a1 lower_thre shold_2_dat a0 76543210 bucket_size _2_data7 bucket_size _2_data6 bucket_size _2_data5 bucket_size _2_data4 bucket_size _2_data3 bucket_size _2_data2 bucket_size _2_data1 bucket_size _2_data0 7654321 0 ------ decay_rate_ 2_data1 decay_rate_ 2_data0
IDT82V3285 wan pl l programming information 90 december 9, 2008 upper_threshold_3_cnfg - up per threshold for leaky bucket configuration 3 lower_threshold_3_c nfg - lower threshold for leaky bucket configuration 3 bucket_size_3_cnfg - bucket size for leaky bucket configuration 3 address: 3dh type: read / write default value: 00000110 bit name description 7 - 0 upper_threshold_3_data[7:0] these bits set an upper threshold for the internal leaky bucket accumulator. when the number of the accumu- lated events is above this threshold, a no-activity alarm is raised. address: 3eh type: read / write default value: 00000100 bit name description 7 - 0 lower_threshold_3_data[7:0] these bits set a lower threshold for the internal leaky bucket accumulator. when the number of the accumu- lated events is below this threshold, the no-activity alarm is cleared. address: 3fh type: read / write default value: 00001000 bit name description 7 - 0 bucket_size_3_data[7:0] these bits set a bucket size for the internal leaky bucket accumulator. if the number of the accumulated events reaches the bucket size, the accumulator will stop increasing even if further events are detected. 76543210 upper_thre shold_3_dat a7 upper_thre shold_3_dat a6 upper_thre shold_3_dat a5 upper_thre shold_3_dat a4 upper_thre shold_3_dat a3 upper_thre shold_3_dat a2 upper_thre shold_3_dat a1 upper_thre shold_3_dat a0 76543210 lower_thre shold_3_dat a7 lower_thre shold_3_dat a6 lower_thre shold_3_dat a5 lower_thre shold_3_dat a4 lower_thre shold_3_dat a3 lower_thre shold_3_dat a2 lower_thre shold_3_dat a1 lower_thre shold_3_dat a0 76543210 bucket_size _3_data7 bucket_size _3_data6 bucket_size _3_data5 bucket_size _3_data4 bucket_size _3_data3 bucket_size _3_data2 bucket_size _3_data1 bucket_size _3_data0
IDT82V3285 wan pl l programming information 91 december 9, 2008 decay_rate_3_cnfg - decay rate fo r leaky bucket configuration 3 in_freq_read_ch_cnfg - input clock frequency read channel selection address: 40h type: read / write default value: xxxxxx01 bit name description 7 - 2 - reserved. 1 - 0 decay_rate_3_data[1:0] these bits set a decay rate for the internal leaky bucket accumulator: 00: the accumulator decreases by 1 in every 128 ms with no event detected. 01: the accumulator decreases by 1 in every 256 ms with no event detected. (default) 10: the accumulator decreases by 1 in every 512 ms with no event detected. 11: the accumulator decreases by 1 in every 1024 ms with no event detected. address: 41h type: read / write default value: xxxx0000 bit name description 7 - 4 - reserved. 3 - 0 in_freq_read_ch[3:0] these bits select an input clock, the frequency of which with respect to the reference clock can be read. 0000: reserved. (default) 0001, 0010: reserved. 0011: in1. 0100: in2. 0101: in3. 0110: in4. 0111, 1000, 1001, 1010: reserved. 1011: in5. 1100, 1101, 1110, 1111: reserved. 76543210 ------ decay_rate_ 3_data1 decay_rate_ 3_data0 7654 3 2 1 0 ---- in_freq_read _ch3 in_freq_read _ch2 in_freq_read _ch1 in_freq_read _ch0
IDT82V3285 wan pl l programming information 92 december 9, 2008 in_freq_read_sts - input clock frequency read value address: 42h type: read default value: 00000000 bit name description 7 - 0 in_freq_value[7:0] these bits represent a 2?s complement signed integer. if the value is multiplied by the value in the freq_mon_factor[3:0] bits (b3~0, 2eh), the frequency of an input clock with respect to the reference clock in ppm will be gotten. the input clock is selected by the in_freq_read_ch[3:0] bits (b3~0, 41h). the value in these bits is updated every 16 seconds, starting when an input clock is selected. 76543210 in_freq_val ue7 in_freq_val ue6 in_freq_val ue5 in_freq_val ue4 in_freq_val ue3 in_freq_val ue2 in_freq_val ue1 in_freq_val ue0
IDT82V3285 wan pl l programming information 93 december 9, 2008 in1_in2_sts - input clock 1 & 2 status address: 44h type: read default value: x110x110 bit name description 7 - reserved. 6 in2_freq_hard_alarm this bit indicates whether in2 is in frequency hard alarm status. 0: no frequency hard alarm. 1: in frequency hard alarm status. (default) 5 in2_no_activity_alarm this bit indicates whether in2 is in no-activity alarm status. 0: no no-activity alarm. 1: in no-activity alarm status. (default) 4 in2_ph_lock_alarm this bit indicates whether in2 is in phase lock alarm status. 0: no phase lock alarm. (default) 1: in phase lock alarm status. if the ph_alarm_timeout bit (b5, 09h) is ?0?, this bit is cleared by writing ?1? to this bit; if the ph_alarm_timeout bit (b5, 09h) is ?1?, this bit is cleared after a period ( = time_out_value[5:0] (b5~0, 08h) x multi_factor[1:0] (b7~6, 08h) in seconds ) which starts from when the alarm is raised. 3 - reserved. 2 in1_freq_hard_alarm this bit indicates whether in1 is in frequency hard alarm status. 0: no frequency hard alarm. 1: in frequency hard alarm status. (default) 1 in1_no_activity_alarm this bit indicates whether in1 is in no-activity alarm status. 0: no no-activity alarm. 1: in no-activity alarm status. (default) 0 in1_ph_lock_alarm this bit indicates whether in1 is in phase lock alarm status. 0: no phase lock alarm. (default) 1: in phase lock alarm status. if the ph_alarm_timeout bit (b5, 09h) is ?0?, this bit is cleared by writing ?1? to this bit; if the ph_alarm_timeout bit (b5, 09h) is ?1?, this bit is cleared after a period ( = time_out_value[5:0] (b5~0, 08h) x multi_factor[1:0] (b7~6, 08h) in seconds ) which starts from when the alarm is raised. 76543210 - in2_freq_har d_alarm in2_no_activi ty_alarm in2_ph_lock_ alarm - in1_freq_har d_alarm in1_no_activi ty_alarm in1_ph_lock_ alarm
IDT82V3285 wan pl l programming information 94 december 9, 2008 in3_in4_sts - input clock 3 & 4 status address: 45h type: read default value: x110x110 bit name description 7-reserved. 6 in4_freq_hard_alarm this bit indicates whether in4 is in frequency hard alarm status. 0: no frequency hard alarm. 1: in frequency hard alarm status. (default) 5 in4_no_activity_alarm this bit indicates whether in4 is in no-activity alarm status. 0: no no-activity alarm. 1: in no-activity alarm status. (default) 4 in4_ph_lock_alarm this bit indicates whether in4 is in phase lock alarm status. 0: no phase lock alarm. (default) 1: in phase lock alarm status. if the ph_alarm_timeout bit (b5, 09h) is ?0?, this bit is cleared by writing ?1? to this bit; if the ph_alarm_timeout bit (b5, 09h) is ?1?, this bit is cleared after a period ( = time_out_value[5:0] (b5~0, 08h) x multi_factor[1:0] (b7~6, 08h) in seconds ) which starts from when the alarm is raised. 3-reserved. 2 in3_freq_hard_alarm this bit indicates whether in3 is in frequency hard alarm status. 0: no frequency hard alarm. 1: in frequency hard alarm status. (default) 1 in3_no_activity_alarm this bit indicates whether in3 is in no-activity alarm status. 0: no no-activity alarm. 1: in no-activity alarm status. (default) 0 in3_ph_lock_alarm this bit indicates whether in3 is in phase lock alarm status. 0: no phase lock alarm. (default) 1: in phase lock alarm status. if the ph_alarm_timeout bit (b5, 09h) is ?0?, this bit is cleared by writing ?1? to this bit; if the ph_alarm_timeout bit (b5, 09h) is ?1?, this bit is cleared after a period ( = time_out_value[5:0] (b5~0, 08h) x multi_factor[1:0] (b7~6, 08h) in seconds ) which starts from when the alarm is raised. 76543210 - in4_freq_har d_alarm in4_no_activi ty_alarm in4_ph_lock_ alarm - in3_freq_har d_alarm in3_no_activi ty_alarm in3_ph_lock_ alarm
IDT82V3285 wan pl l programming information 95 december 9, 2008 in5_sts - input clock 5 status address: 48h type: read default value: x110x110 bit name description 7 - 3 - reserved. 2 in5_freq_hard_alarm this bit indicates whether in5 is in frequency hard alarm status. 0: no frequency hard alarm. 1: in frequency hard alarm status. (default) 1 in5_no_activity_alarm this bit indicates whether in5 is in no-activity alarm status. 0: no no-activity alarm. 1: in no-activity alarm status. (default) 0 in5_ph_lock_alarm this bit indicates whether in5 is in phase lock alarm status. 0: no phase lock alarm. (default) 1: in phase lock alarm status. if the ph_alarm_timeout bit (b5, 09h) is ?0?, this bit is cleared by writing ?1? to this bit; if the ph_alarm_timeout bit (b5, 09h) is ?1?, this bit is cleared after a period ( = time_out_value[5:0] (b5~0, 08h) x multi_factor[1:0] (b7~6, 08h) in seconds ) which starts from when the alarm is raised. 76543210 ----- in5_freq_ha rd_alarm in5_no_activ ity_alarm in5_ph_lock _alarm
IDT82V3285 wan pl l programming information 96 december 9, 2008 7.2.5 t0 / t4 dpll input clock selection registers input_valid1_sts - input clocks validity 1 input_valid2_sts - input clocks validity 2 remote_input_valid1_cnfg - input clocks validity configuration 1 address: 4ah type: read default value: 00000000 bit name description 7 - 6 - reserved. 5 - 2 inn this bit indicates the validity of the corresponding inn. here n is any of 4 to 1. 0: invalid. (default) 1: valid. 1 - 0 - reserved. address: 4bh type: read default value: xx000000 bit name description 7 - 3 - reserved. 2in5 this bit indicates the validity of in5. 0: invalid. (default) 1: valid. 1 - 0 - reserved. address: 4ch type: read / write default value: 11111111 bit name description 7 - 6 - reserved. 5 - 2 inn_valid this bit controls whether the corresponding inn is allowed to be locked for automatic selection. here n is any one of 4 to 1. 0: enabled. 1: disabled. (default) 1 - 0 - reserved. 76543210 - - in4 in3 in2 in1 - - 76543210 -----in5-- 76543210 - - in4_valid in3_valid in2_valid in1_valid - -
IDT82V3285 wan pl l programming information 97 december 9, 2008 remote_input_valid2_cnfg - input clocks validity configuration 2 priority_table1_sts - priority status 1 * address: 4dh type: read / write default value: xx111111 bit name description 7 - 3 - reserved. 2in5_valid this bit controls whether in5 is allowed to be locked for automatic selection. 0: enabled. 1: disabled. (default) 1 - 0 - reserved. address: 4eh type: read default value: 00000000 bit name description 7 - 4 highest_priority_validated[3:0] these bits indicate a qualified input clock with the highest priority. 0000: no input clock is qualified. (default) 0001, 0010: reserved. 0011: in1. 0100: in2. 0101: in3. 0110: in4. 0111, 1000, 1001, 1010: reserved. 1011: in5. 1100, 1101, 1110, 1111: reserved. note that the input clock is indicated by these bits only when the corresponding inn (b5-2, 4ch) or inn (b2, 4dh) bit is ?0?. 3 - 0 currently_selected_input[3:0] these bits indicate the t0/t4 selected input clock. 0000: no input clock is selected; or the t4 selected input clock is the t0 dpll output. (default) 0001, 0010: reserved. 0011: in1 is selected. 0100: in2 is selected. 0101: in3 is selected. 0110: in4 is selected. 0111, 1000, 1001, 1010: reserved. 1011: in5 is selected. 1100, 1101, 1110, 1111: reserved. note that the input clock is indicated by these bits only when the corresponding inn (b5-2, 4ch) or inn (b2, 4dh) bit is ?0?. 76543210 -----in5_valid-- 76543210 highest_pri ority_valida ted3 highest_pri ority_valida ted2 highest_pri ority_valida ted1 highest_pri ority_valida ted0 currently_s elected_inp ut3 currently_s elected_inp ut2 currently_s elected_inp ut1 currently_s elected_inp ut0
IDT82V3285 wan pl l programming information 98 december 9, 2008 priority_table2_sts - priority status 2 * address: 4fh type: read default value: 00000000 bit name description 7 - 4 third_highest_priority_validated[3:0] these bits indicate a qualified input clock with the third highest priority. 0000: no input clock is qualified. (default) 0001, 0010: reserved. 0011: in1. 0100: in2. 0101: in3. 0110: in4. 0111, 1000, 1001, 1010: reserved. 1011: in5. 1100, 1101, 1110, 1111: reserved. note that the input clock is indicated by these bits only when the corresponding inn (b5-2, 4ch) or inn (b2, 4dh) bit is ?0?. 3 - 0 second_highest_priority_validated[3:0] these bits indicate a qualified input clock with the second highest priority. 0000: no input clock is qualified. (default) 0001, 0010: reserved. 0011: in1. 0100: in2. 0101: in3. 0110: in4. 0111, 1000, 1001, 1010: reserved. 1011: in5. 1100, 1101, 1110, 1111: reserved. note that the input clock is indicated by these bits only when the corresponding inn (b5-2, 4ch) or inn (b2, 4dh) bit is ?0?. 76543210 third_highe st_priority_ validated3 third_highe st_priority_ validated2 third_highe st_priority_ validated1 third_highe st_priority_ validated0 second_high est_priority _validated3 second_high est_priority _validated2 second_high est_priority _validated1 second_high est_priority _validated0
IDT82V3285 wan pl l programming information 99 december 9, 2008 t0_input_sel_cnfg - t0 select ed input clock configuration address: 50h type: read / write default value: xxxx0000 bit name description 7 - 4 - reserved. 3 - 0 t0_input_sel[3:0] this bit determines t0 input clock selection. it is valid only when the ext_sw bit (b4, 0bh) is ?0?. 0000: automatic selection. (default) 0001, 0010: reserved. 0011: forced selection - in1 is selected. 0100: forced selection - in2 is selected. 0101: forced selection - in3 is selected. 0110: forced selection - in4 is selected. 0111, 1000, 1001, 1010: reserved. 1011: forced selection - in5 is selected. 1100, 1101, 1110, 1111: reserved. 7654 3 2 1 0 - - - - t0_input_sel3 t0_input_sel2 t0_input_sel1 t0_input_sel0
IDT82V3285 wan pl l programming information 100 december 9, 2008 t4_input_sel_cnfg - t4 select ed input clock configuration address: 51h type: read / write default value: x0000000 bit name description 7-reserved. 6 t4_lock_t0 this bit determines whether the t4 dpll locks to a t0 dpll output or locks independently from the t0 dpll. 0: independently from the t0 path. (default) 1: locks to a 77.76 mhz or 8 khz signal from the t0 dpll 77.76 mhz path. 5 t0_for_t4 this bit is valid only when the t4_lock_t0 bit (b6, 51h) is ?1?. it determines whether a 77.76 mhz or 8 khz signal from the t0 dpll 77.76 mhz path is selected by the t4 dpll. 0: 77.76 mhz. (default) 1: 8 khz. 4 t4_test_t0_ph this bit determines whether t4 selected input clock is compared with the feedback signal of the t4 dpll for t4 dpll locking or is compared with the t0 selected input clock to get the phase difference between t0 and t4 selected input clocks. 0: the t4 dpll output. (default) 1: the t0 selected input clock. 3 - 0 t4_input_sel[3:0] these bits are valid only when the t4_lock_t0 bit (b6, 51h) is ?0?. they determines the t4 dpll input clock selection. 0000: automatic selection. (default) 0001, 0010: reserved. 0011: forced selection - in1 is selected. 0100: forced selection - in2 is selected. 0101: forced selection - in3 is selected. 0110: forced selection - in4 is selected. 0111, 1000, 1001, 1010: reserved. 1011: forced selection - in5 is selected. 1100, 1101, 1110, 1111: reserved. 76543210 - t4_lock_t0 t0_for_t4 t4_test_t0_ph t4_input_sel3 t4_input_sel2 t4_input_sel1 t4_input_sel0
IDT82V3285 wan pl l programming information 101 december 9, 2008 7.2.6 t0 / t4 dpll state machine control registers operating_sts - dpll operating status address: 52h type: read default value: 10000001 bit name description 7 ex_sync_alarm_mon this bit indicates whether the frame sync input signal is in external sync alarm status. 0: no external sync alarm. 1: in external sync alarm status. (default) 6 t4_dpll_lock this bit indicates the t4 dpll locking status. 0: unlocked. (default) 1: locked. 5 t0_dpll_soft_freq_alarm this bit indicates whether the t0 dpll is in soft alarm status. 0: no t0 dpll soft alarm. (default) 1: in t0 dpll soft alarm status. 4 t4_dpll_soft_freq_alarm this bit indicates whether the t4 dpll is in soft alarm status. 0: no t4 dpll soft alarm. (default) 1: in t4 dpll soft alarm status. 3 t0_dpll_lock this bit indicates the t0 dpll locking status. 0: unlocked. (default) 1: locked. 2 - 0 t0_dpll_operating_mode[2:0] these bits indicate the current operating mode of t0 dpll. 000: reserved. 001: free-run. (default) 010: holdover. 011: reserved. 100: locked. 101: pre-locked2. 110: pre-locked. 111: lost-phase. 76543210 ex_sync_ala rm_mon t4_dpll_lo ck t0_dpll_soft _freq_alarm t4_dpll_soft _freq_alarm t0_dpll_lo ck t0_dpll_oper ating_mode2 t0_dpll_oper ating_mode1 t0_dpll_oper ating_mode0
IDT82V3285 wan pl l programming information 102 december 9, 2008 t0_operating_mode_cnfg - t0 dp ll operating mode configuration t4_operating_mode_cnfg - t4 dp ll operating mode configuration address: 53h type: read / write default value: xxxxx000 bit name description 7 - 3 - reserved. 2 - 0 t0_operating_mode[2:0] these bits control the t0 dpll operating mode. 000: automatic. (default) 001: forced - free-run. 010: forced - holdover. 011: reserved. 100: forced - locked. 101: forced - pre-locked2. 110: forced - pre-locked. 111: forced - lost-phase. address: 54h type: read / write default value: xxxxx000 bit name description 7 - 3 - reserved. 2 - 0 t4_operating_mode[2:0] these bits control the t4 dpll operating mode. 000: automatic. (default) 001: forced - free-run. 010: forced - holdover. 011: reserved. 100: forced - locked. 101, 110, 111: reserved. 76543 2 1 0 -----t0_operating_mode 2 t0_operating_mode1 t 0_operating_mode0 76543 2 1 0 -----t4_operating_mode2t4_operating_mode1t4_operating_mode0
IDT82V3285 wan pl l programming information 103 december 9, 2008 7.2.7 t0 / t4 dpll & apll configuration registers t0_dpll_apll_path_cnfg - t0 dpll & apll path configuration address: 55h type: read / write default value: 00000x0x bit name description 7 - 4 t0_apll_path[3:0] these bits select an input to the t0 apll. 0000: the output of t0 dpll 77.76 mhz path. (default) 0001: the output of t0 dpll 12e1/24t1/e3/t3 path. 0010: the output of t0 dpll 16e1/16t1 path. 0011: the output of t0 dpll gsm/obsai/16e1/16t1 path. 0100: the output of t4 dpll 77.76 mhz path. 0101: the output of t4 dpll 12e1/24t1/e3/t3 path. 0110: the output of t4 dpll 16e1/16t1 path. 0111: the output of t4 dpll gsm/gps/16e1/16t1 path. 1xxx: reserved. 3 - 2 t0_gsm_obsai_16e1_16t1_sel[1:0] these bits select an output clock from the t0 dpll gsm/obsai/16e1/16t1 path. 00: 16e1. 01: 16t1. 10: gsm. 11: obsai. the default value of the t0_gsm_obsai_16e1_1 6t1_sel0 bit is determined by the sonet/ sdh pin dur- ing reset. 1 - 0 t0_12e1_24t1_e3_t3_sel[1:0] these bits select an output clock from the t0 dpll 12e1/24t1/e3/t3 path. 00: 12e1. 01: 24t1. 10: e3. 11: t3. the default value of the t0_12e1_24t1_e3_t3_sel0 bit is determined by the sonet/ sdh pin during reset. 7654 3 2 1 0 t0_apll_path 3 t0_apll_pa th2 t0_apll_pa th1 t0_apll_pa th0 t0_gsm_obsai_ 16e1_16t1_sel1 t0_gsm_obsai_ 16e1_16t1_sel0 t0_12e1_24t1_ e3_t3_sel1 t0_12e1_24t1_ e3_t3_sel0
IDT82V3285 wan pl l programming information 104 december 9, 2008 t0_dpll_start_bw_damping_cnfg - t0 dpll start bandwidth & damping factor configuration address: 56h type: read / write default value: 01101111 bit name description 7 - 5 t0_dpll_start_damping[2:0] these bits set the starting damping factor for t0 dpll. 000: reserved. 001: 1.2. 010: 2.5. 011: 5. (default) 100: 10. 101: 20. 110, 111: reserved. 4 - 0 t0_dpll_start_bw[4:0] these bits set the starting bandwidth for t0 dpll. 00000: 0.5 mhz. 00001: 1 mhz. 00010: 2 mhz. 00011: 4 mhz. 00100: 8 mhz. 00101: 15 mhz. 00110: 30 mhz. 00111: 60 mhz. 01000: 0.1 hz. 01001: 0.3 hz. 01010: 0.6 hz. 01011: 1.2 hz. 01100: 2.5 hz. 01101: 4 hz. 01110: 8 hz. 01111: 18 hz. (default) 10000: 35 hz. 10001: 70 hz. 10010: 560 hz. 10011 ~ 11111: reserved. 76543210 t0_dpll_sta rt_damping2 t0_dpll_sta rt_damping1 t0_dpll_sta rt_damping0 t0_dpll_sta rt_bw4 t0_dpll_sta rt_bw3 t0_dpll_sta rt_bw2 t0_dpll_sta rt_bw1 t0_dpll_sta rt_bw0
IDT82V3285 wan pl l programming information 105 december 9, 2008 t0_dpll_acq_bw_damping_cnfg - t0 dpll acquisit ion bandwidth & damping factor configuration address: 57h type: read / write default value: 01101111 bit name description 7 - 5 t0_dpll_acq_damping[2:0] these bits set the acquisition damping factor for t0 dpll. 000: reserved. 001: 1.2. 010: 2.5. 011: 5. (default) 100: 10. 101: 20. 110, 111: reserved. 4 - 0 t0_dpll_acq_bw[4:0] these bits set the acquisition bandwidth for t0 dpll. 00000: 0.5 mhz. 00001: 1 mhz. 00010: 2 mhz. 00011: 4 mhz. 00100: 8 mhz. 00101: 15 mhz. 00110: 30 mhz. 00111: 60 mhz. 01000: 0.1 hz. 01001: 0.3 hz. 01010: 0.6 hz. 01011: 1.2 hz. 01100: 2.5 hz. 01101: 4 hz. 01110: 8 hz. 01111: 18 hz. (default) 10000: 35 hz. 10001: 70 hz. 10010: 560 hz. 10011 ~ 11111: reserved. 76543210 t0_dpll_acq _damping2 t0_dpll_acq _damping1 t0_dpll_acq _damping0 t0_dpll_acq _bw4 t0_dpll_acq _bw3 t0_dpll_acq _bw2 t0_dpll_acq _bw1 t0_dpll_acq _bw0
IDT82V3285 wan pl l programming information 106 december 9, 2008 t0_dpll_locked_bw_damping_cnfg - t0 dpll locked bandwidth & damping factor configuration address: 58h type: read / write default value: 01101011 bit name description 7 - 5 t0_dpll_locked_damping[2:0] these bits set the locked damping factor for t0 dpll. 000: reserved. 001: 1.2. 010: 2.5. 011: 5. (default) 100: 10. 101: 20. 110, 111: reserved. 4 - 0 t0_dpll_locked_bw[4:0] these bits set the locked bandwidth for t0 dpll. 00000: 0.5 mhz. 00001: 1 mhz. 00010: 2 mhz. 00011: 4 mhz. 00100: 8 mhz. 00101: 15 mhz. 00110: 30 mhz. 00111: 60 mhz. 01000: 0.1 hz. 01001: 0.3 hz. 01010: 0.6 hz. 01011: 1.2 hz. (default) 01100: 2.5 hz. 01101: 4 hz. 01110: 8 hz. 01111: 18 hz. 10000: 35 hz. 10001: 70 hz. 10010: 560 hz. 10011 ~ 11111: reserved. 7 6 5 43210 t0_dpll_lock ed_damping2 t0_dpll_lock ed_damping1 t0_dpll_lock ed_damping0 t0_dpll_loc ked_bw4 t0_dpll_loc ked_bw3 t0_dpll_loc ked_bw2 t0_dpll_loc ked_bw1 t0_dpll_loc ked_bw0
IDT82V3285 wan pl l programming information 107 december 9, 2008 t0_bw_overshoot_cnfg - t0 dpll ba ndwidth overshoot configuration address: 59h type: read / write default value: 1xxx1xxx bit name description 7 auto_bw_sel this bit determines whether starting or acquisition bandwidth / damping factor is used for t0 dpll. 0: the starting and acquisition bandwidths / damping factors are not used. only the locked bandwidth / damping factor is used regardless of the t0 dpll locking stage. 1: the starting, acquisition or locked bandwidth / damping factor is used automatically depending on different t0 dpll locking stages. (default) 6 - 4 - reserved. 3 t0_limt this bit determines whether the integral path value is frozen when the t0 dpll hard limit is reached. 0: not frozen. 1: frozen. it will minimize the subsequent overshoot when t0 dpll is pulling in. (default) 2 - 0 - reserved. 7 6 5 43210 auto_bw_sel - - - t0_limt - - -
IDT82V3285 wan pl l programming information 108 december 9, 2008 phase_loss_coarse_limit_cnfg - phase loss coarse detector limit configuration * address: 5ah type: read / write default value: 10000101 bit name description 7 coarse_ph_los_limt_en this bit controls whether the occurrence of the coarse phase loss will result in the t0/t4 dpll being unlocked. 0: disabled. 1: enabled. (default) 6 wide_en refer to the description of the multi_ph_8k_4k_2k_en bit (b4, 5ah). 5 multi_ph_app this bit determines whether the pfd output of t0/t4 dpll is limited to 1 ui or is limited to the coarse phase limit. 0: limited to 1 ui. (default) 1: limited to the coarse phase limit. when the selected input clock is of 2 khz, 4 khz or 8 khz, the coarse phase limit depends on the multi_ph_8k_4k_2k_en bit, the wide_en bit and the ph_los_coarse_limt[3:0] bits; when the selected input clock is of other frequencies than 2 khz, 4 khz and 8 khz, the coarse phase limit depends on the wide_en bit and the ph_los_coarse_limt[3:0] bits. refer to the description of the multi_ph_8k_4k_2k_en bit (b4, 5ah) for details. 4 multi_ph_8k_4k_2k_en this bit, together with the wide_en bit (b6, 5ah) and th e ph_los_coarse_limt[3:0] bits (b3~0, 5ah), determines the coarse phase limit when the selected input clock is of 2 khz, 4 khz or 8 khz. when the selected input clock is of other frequen - cies than 2 khz, 4 khz and 8 khz, the coarse phase limi t depends on the wide_en bit and the ph_los_coarse_limt[3:0] bits. 3 - 0 ph_los_coarse_limt[3:0] these bit set the coarse phase limit. the limit is used only in some cases. refer to the description of the multi_ph_8k_4k_2k_en bit (b4, 5ah). 0000: 1 ui. 0001: 3 ui. 0010: 7 ui. 0011: 15 ui. 0100: 31 ui. 0101: 63 ui. (default) 0110: 127 ui. 0111: 255 ui. 1000: 511 ui. 1001: 1023 ui (t0); reserved (t4). 1010-1111: reserved. 7 6 5 43210 coarse_ph_l os_limt_en wide_en multi_ph_app multi_ph_8k_ 4k_2k_en ph_los_coa rse_limt3 ph_los_coa rse_limt2 ph_los_coa rse_limt1 ph_los_coa rse_limt0 selected input clock multi_ph_8k_4k_2k_en wide_en coarse phase limit 2 khz, 4 khz or 8 khz 0 don?t-care 1 ui 1 01 ui 1 set by the ph_los_coarse_limt[3:0] bits (b3~0, 5ah). other than 2 khz, 4 khz and 8 khz don?t-care 01 ui 1 set by the ph_los_coarse_limt[3:0] bits (b3~0, 5ah).
IDT82V3285 wan pl l programming information 109 december 9, 2008 phase_loss_fine_limit_cnfg - phase loss fine detector limit configuration * address: 5bh type: read / write default value: 10xxx010 bit name description 7 fine_ph_los_limt_en this bit controls whether the occurrence of the fine phase loss will result in the t0/t4 dpll being unlocked. 0: disabled. 1: enabled. (default) 6 fast_los_sw the value in this bit can be switched only when it is available for t0 path; this bit is always ?1? when it is available for t4 path. this bit controls whether the occurrence of the fast loss will result in the t0/t4 dpll being unlocked. 0: does not result in the t0 dpll being unlocked. t0 dpll will enter temp-holdover mode automatically. (default) 1: results in the t0/t4 dpll being unlocked. for t0 path, t0 dpll will enter lost-phase mode if the t0 dpll operat- ing mode is switched automatically. 5 - 3 - reserved. 2 - 0 ph_los_fine_limt[2:0] these bits set a fine phase limit. 000: 0. 001: (45 ~ 90 ). 010: (90 ~ 180 ). (default) 011: (180 ~ 360 ). 100: (20 ns ~ 25 ns). 101: (60 ns ~ 65 ns). 110: (120 ns ~ 125 ns). 111: (950 ns ~ 955 ns). 76543210 fine_ph_los_ limt_en fast_los_sw - - - ph_los_fine _limt2 ph_los_fine _limt1 ph_los_fine _limt0
IDT82V3285 wan pl l programming information 110 december 9, 2008 t0_holdover_mode_cnfg - t0 dpll holdover mode configuration t0_holdover_freq[7:0]_cnfg - t0 dpll holdover frequen cy configuration 1 address: 5ch type: read / write default value: 010001xx bit name description 7 man_holdover refer to the descriptio n of the fast_avg bit (b5, 5ch). 6 auto_avg refer to the description of the fast_avg bit (b5, 5ch). 5 fast_avg this bit, together with the auto_avg bit (b6, 5ch) and the man_holdover bit (b7, 5ch), determines a fre- quency offset acquiring method in t0 dpll holdover mode. 4 read_avg this bit controls the holdover frequency offset reading, which is read from the t0_holdover_freq[23:0] bits (5fh ~ 5dh). 0: the value read from the t0_holdover_freq[23:0] bits (5fh ~ 5dh) is equal to the one written to them. (default) 1: the value read from the t0_holdover_freq[23:0] bits (5fh ~ 5dh) is not equal to the one written to them. the value is acquired by automatic slow averaged method if the fast_avg bit (b5, 5ch) is ?0?; or is acquired by automatic fast averaged method if the fast_avg bit (b5, 5ch) is ?1?. 3 - 2 temp_holdover_mode[1:0] these bits determine the frequency offset acquiring method in t0 dpll temp-holdover mode. 00: the method is the same as that used in t0 dpll holdover mode. 01: automatic instantaneous. (default) 10: automatic fast averaged. 11: automatic slow averaged. 1 - 0 - reserved. address: 5dh type: read / write default value: 00000000 bit name description 7 - 0 t0_holdover_freq[7:0] refer to the description of the t0_holdover_freq[23:16] bits (b7~0, 5fh). 7 6 5 43210 man_holdov er auto_avg fast_avg read_avg temp_holdo ver_mode1 temp_holdo ver_mode0 -- man_holdover auto_avg fast_avg fr equency offset acquiring method 0 0 don?t-care automatic instantaneous 1 0 automatic slow averaged (default) 1 automatic fast averaged 1 don?t-care manual 7 6 5 43210 t0_holdover _freq7 t0_holdover _freq6 t0_holdover _freq5 t0_holdove r_freq4 t0_holdove r_freq3 t0_holdove r_freq2 t0_holdove r_freq1 t0_holdove r_freq0
IDT82V3285 wan pl l programming information 111 december 9, 2008 t0_holdover_freq[15:8]_cnf g - t0 dpll holdover frequency configuration 2 t0_holdover_freq[23:16]_cnfg - t0 dpll holdover frequen cy configuration 3 address: 5eh type: read / write default value: 00000000 bit name description 7 - 0 t0_holdover_freq[15:8] refer to the description of the t0_holdover_freq[23:16] bits (b7~0, 5fh). address: 5fh type: read / write default value: 00000000 bit name description 7 - 0 t0_holdover_freq[23:16] the t0_holdover_freq[23:0] bits represent a 2?s complement signed integer. in t0 dpll holdover mode, the value written to these bits multiplied by 0.000011 is the frequency offset set manu- ally; the value read from these bits multiplied by 0.000011 is the frequency offset automatically slow or fast aver- aged or manually set, as determined by the read_a vg bit (b4, 5ch) and the fast_avg bit (b5, 5ch). 7 6 5 43210 t0_holdover _freq15 t0_holdover _freq14 t0_holdover _freq13 t0_holdove r_freq12 t0_holdove r_freq11 t0_holdove r_freq10 t0_holdove r_freq9 t0_holdove r_freq8 7 6 5 43210 t0_holdover _freq23 t0_holdover _freq22 t0_holdover _freq21 t0_holdove r_freq20 t0_holdove r_freq19 t0_holdove r_freq18 t0_holdove r_freq17 t0_holdove r_freq16
IDT82V3285 wan pl l programming information 112 december 9, 2008 t4_dpll_apll_path_cnfg - t4 dpll & apll path configuration address: 60h type: read / write default value: 01000x0x bit name description 7 - 4 t4_apll_path[3:0] these bits select an input to the t4 apll. 0000: the output of t0 dpll 77.76 mhz path. 0001: the output of t0 dpll 12e1/24t1/e3/t3 path. 0010: the output of t0 dpll 16e1/16t1 path. 0011: the output of t0 dpll gsm/obsai/16e1/16t1 path. 0100: the output of t4 dpll 77.76 mhz path. (default) 0101: the output of t4 dpll 12e1/24t1/e3/t3 path. 0110: the output of t4 dpll 16e1/16t1 path. 0111: the output of t4 dpll gsm/gps/16e1/16t1 path. 1xxx: reserved. 3 - 2 t4_gsm_gps_16e1_16t1_sel[1:0] these bits select an output clock from the t4 dpll gsm/gps/16e1/16t1 path. 00: 16e1. 01: 16t1. 10: gsm. 11: gps. the default value of the t0_gsm_gps_16e1_16t1_sel0 bit is determined by the sonet/ sdh pin during reset. 1 - 0 t4_12e1_24t1_e3_t3_sel[1:0] these bits select an output clock from the t4 dpll 12e1/24t1/e3/t3 path. 00: 12e1. 01: 24t1. 10: e3. 11: t3. the default value of the t4_12e1_24t1_e3_t3_sel0 bit is determined by the sonet/ sdh pin during reset. 7654 3 2 1 0 t4_apll_path 3 t4_apll_pa th2 t4_apll_pa th1 t4_apll_pa th0 t4_gsm_gps_16 e1_16t1_sel1 t4_gsm_gps_16 e1_16t1_sel0 t4_12e1_24t1_ e3_t3_sel1 t4_12e1_24t1_ e3_t3_sel0
IDT82V3285 wan pl l programming information 113 december 9, 2008 t4_dpll_locked_bw_damping_cnfg - t4 dpll locked bandwidth & damping factor configuration current_dpll_freq[7:0]_sts - dpll current frequency status 1 * current_dpll_freq[15:8]_sts - dpll current frequency status 2 * address: 61h type: read / write default value: 011xxx00 bit name description 7 - 5 t4_dpll_locked_damping[2:0] these bits set the locked damping factor for t4 dpll. 000: reserved. 001: 1.2. 010: 2.5. 011: 5. (default) 100: 10. 101: 20. 110, 111: reserved. 4 - 2 - reserved. 1 - 0 t4_dpll_locked_bw[1:0] these bits set the locked bandwidth for t4 dpll. 00: 18 hz. (default) 01: 35 hz. 10: 70 hz. 11: 560 hz. address: 62h type: read default value: 00000000 bit name description 7 - 0 current_dpll_freq[7:0] refer to the description of the current_dpll_freq[23:16] bits (b7~0, 64h). address: 63h type: read default value: 00000000 bit name description 7 - 0 current_dpll_freq[15:8] refer to the description of the current_dpll_freq[23:16] bits (b7~0, 64h). 7 6 5 43210 t4_dpll_lock ed_damping2 t4_dpll_lock ed_damping1 t4_dpll_lock ed_damping0 --- t4_dpll_loc ked_bw1 t4_dpll_loc ked_bw0 76543210 current_dp ll_freq7 current_dp ll_freq6 current_dp ll_freq5 current_dp ll_freq4 current_dp ll_freq3 current_dp ll_freq2 current_dp ll_freq1 current_dp ll_freq0 76543210 current_dp ll_freq15 current_dp ll_freq14 current_dp ll_freq13 current_dp ll_freq12 current_dp ll_freq11 current_dp ll_freq10 current_dp ll_freq9 current_dp ll_freq8
IDT82V3285 wan pl l programming information 114 december 9, 2008 current_dpll_freq[23:16]_sts - dpll current frequency status 3 * dpll_freq_soft_limit_cnfg - dpll soft limit configuration dpll_freq_hard_limit[7:0]_cnfg - dp ll hard limit configuration 1 address: 64h type: read default value: 00000000 bit name description 7 - 0 current_dpll_freq[23:16] the current_dpll_freq[23:0] bits represent a 2?s complement signed integer. if the value in these bits is mul- tiplied by 0.000011, the current frequency offset of the t0/t4 dpll output in ppm with respect to the master clock will be gotten. address: 65h type: read / write default value: 10001100 bit name description 7 freq_limt_ph_los this bit determines whether the t0/t4 dpll in hard alarm status will result in its being unlocked. 0: disabled. 1: enabled. (default) 6 - 0 dpll_freq_soft_limt[6:0] these bits represent an unsigned integer. if the value is multiplied by 0.724, the dpll soft limit for t0 and t4 paths in ppm will be gotten. the dpll soft limit is symmetrical about zero. address: 66h type: read / write default value: 10101011 bit name description 7 - 0 dpll_freq_hard_limt[7:0] refer to the description of the dpll_freq_hard_limt[15:8] bits (b7~0, 67h). 76543210 current_dp ll_freq23 current_dp ll_freq22 current_dp ll_freq21 current_dp ll_freq20 current_dp ll_freq19 current_dp ll_freq18 current_dp ll_freq17 current_dp ll_freq16 76543210 freq_limt_p h_los dpll_freq_s oft_limt6 dpll_freq_s oft_limt5 dpll_freq_s oft_limt4 dpll_freq_s oft_limt3 dpll_freq_s oft_limt2 dpll_freq_s oft_limt1 dpll_freq_s oft_limt0 76543210 dpll_freq_h ard_limt7 dpll_freq_h ard_limt6 dpll_freq_h ard_limt5 dpll_freq_h ard_limt4 dpll_freq_h ard_limt3 dpll_freq_h ard_limt2 dpll_freq_h ard_limt1 dpll_freq_h ard_limt0
IDT82V3285 wan pl l programming information 115 december 9, 2008 dpll_freq_hard_limit[15:8]_cnfg - dp ll hard limit configuration 2 current_dpll_phase[7:0]_sts - dpll current phase status 1 * current_dpll_phase[15:8]_sts - dpll current phase status 2 * address: 67h type: read / write default value: 00011001 bit name description 7 - 0 dpll_freq_hard_limt[15:8] the dpll_freq_hard_limt[15:0] bits represent an unsigned integer. if the value is multiplied by 0.0014, the dpll hard limit for t0 and t4 paths in ppm will be gotten. the dpll hard limit is symmetrical about zero. address: 68h type: read default value: 00000000 bit name description 7 - 0 current_ph_data[7:0] refer to the description of the current_ph_data[15:8] bits (b7~0, 69h). address: 69h type: read default value: 00000000 bit name description 7 - 0 current_ph_data[15:8] the current_ph_data[15:0] bits represent a 2?s complement signed integer. if the value is multiplied by 0.61, the averaged phase error of the t0/t4 dpll feedback with respect to the selected input clock in ns will be gotten. 76543210 dpll_freq_h ard_limt15 dpll_freq_h ard_limt14 dpll_freq_h ard_limt13 dpll_freq_h ard_limt12 dpll_freq_h ard_limt11 dpll_freq_h ard_limt10 dpll_freq_h ard_limt9 dpll_freq_h ard_limt8 76543210 current_ph _data7 current_ph _data6 current_ph _data5 current_ph _data4 current_ph _data3 current_ph _data2 current_ph _data1 current_ph _data0 76543210 current_ph _data15 current_ph _data14 current_ph _data13 current_ph _data12 current_ph _data11 current_ph _data10 current_ph _data9 current_ph _data8
IDT82V3285 wan pl l programming information 116 december 9, 2008 t0_t4_apll_bw_cnfg - t0 / t4 apll bandwidth configuration address: 6ah type: read / write default value: xx01xx01 bit name description 7 - 6 - reserved. 5 - 4 t0_apll_bw[1:0] these bits set the bandwidth for t0 apll. 00: 100 khz. 01: 500 khz. (default) 10: 1 mhz. 11: 2 mhz. 3 - 2 - reserved. 1 - 0 t4_apll_bw[1:0] these bits set the bandwidth for t4 apll. 00: 100 khz. 01: 500 khz. (default) 10: 1 mhz. 11: 2 mhz. 76543210 - - t0_apll_bw1 t0_apll_bw0 - - t4_apll_bw1 t4_apll_bw0
IDT82V3285 wan pl l programming information 117 december 9, 2008 7.2.8 output configuration registers out1_freq_cnfg - output cloc k 1 frequency configuration address: 6dh type: read / write default value: 00001000 bit name description 7 - 4 out1_path_sel[3:0] these bits select an input to out1. 0000 ~ 0011: the output of t0 apll. (default: 0000) 0100: the output of t0 dpll 77.76 mhz path. 0101: the output of t0 dpll 12e1/24t1/e3/t3 path. 0110: the output of t0 dpll 16e1/16t1 path. 0111: the output of t0 dpll gsm/obsai/16e1/16t1 path. 1000 ~ 1011: the output of t4 apll. 1100: the output of t4 dpll 77.76 mhz path. 1101: the output of t4 dpll 12e1/24t1/e3/t3 path. 1110: the output of t4 dpll 16e1/16t1 path. 1111: the output of t4 dpll gsm/gps/16e1/16t1 path. 3 - 0 out1_divider[3:0] these bits select a division factor of the divider for out1. the output frequency is determined by the division factor and the signal derived from t0/t4 dpll or t0/t4 apll output (selected by the out1_path_sel[3:0] bits (b7~4, 6dh)). if the signal is derived from one of the t0/t4 dpll outputs, please refer to table 24 for the division factor selection. if the signal is derived from the t0/t4 apll output, please refer to table 25 for the division factor selection. 76543210 out1_path_s el3 out1_path_s el2 out1_path_s el1 out1_path_s el0 out1_divider 3 out1_divider 2 out1_divider 1 out1_divider 0
IDT82V3285 wan pl l programming information 118 december 9, 2008 out2_freq_cnfg - output cloc k 2 frequency configuration address: 6eh type: read / write default value: 00000110 bit name description 7 - 4 out2_path_sel[3:0] these bits select an input to out2. 0000 ~ 0011: the output of t0 apll. (default: 0000) 0100: the output of t0 dpll 77.76 mhz path. 0101: the output of t0 dpll 12e1/24t1/e3/t3 path. 0110: the output of t0 dpll 16e1/16t1 path. 0111: the output of t0 dpll gsm/obsai/16e1/16t1 path. 1000 ~ 1011: the output of t4 apll. 1100: the output of t4 dpll 77.76 mhz path. 1101: the output of t4 dpll 12e1/24t1/e3/t3 path. 1110: the output of t4 dpll 16e1/16t1 path. 1111: the output of t4 dpll gsm/gps/16e1/16t1 path. 3 - 0 out2_divider[3:0] these bits select a division factor of the divider for out2. the output frequency is determined by the division factor and the signal derived from t0/t4 dpll or t0/t4 apll output (selected by the out2_path_sel[3:0] bits (b7~4, 6eh)). if the signal is derived from one of the t0/t4 dpll outputs, please refer to table 24 for the division factor selection. if the signal is derived from the t0/t4 apll output, please refer to table 25 for the division factor selection. 76543210 out2_path_s el3 out2_path_s el2 out2_path_s el1 out2_path_s el0 out2_divider 3 out2_divider 2 out2_divider 1 out2_divider 0
IDT82V3285 wan pl l programming information 119 december 9, 2008 out3_freq_cnfg - output cloc k 3 frequency configuration address: 6fh type: read / write default value: 00000100 bit name description 7 - 4 out3_path_sel[3:0] these bits select an input to out3. 0000 ~ 0011: the output of t0 apll. (default: 0000) 0100: the output of t0 dpll 77.76 mhz path. 0101: the output of t0 dpll 12e1/24t1/e3/t3 path. 0110: the output of t0 dpll 16e1/16t1 path. 0111: the output of t0 dpll gsm/obsai/16e1/16t1 path. 1000 ~ 1011: the output of t4 apll. 1100: the output of t4 dpll 77.76 mhz path. 1101: the output of t4 dpll 12e1/24t1/e3/t3 path. 1110: the output of t4 dpll 16e1/16t1 path. 1111: the output of t4 dpll gsm/gps/16e1/16t1 path. 3 - 0 out3_divider[3:0] these bits select a division factor of the divider for out3. the output frequency is determined by the division factor and the signal derived from t0/t4 dpll or t0/t4 apll output (selected by the out3_path_sel[3:0] bits (b7~4, 6fh)). if the signal is derived from one of the t0/t4 dpll outputs, please refer to table 24 for the division factor selection. if the signal is derived from the t0/t4 apll output, please refer to table 25 for the division factor selection. 76543210 out3_path_s el3 out3_path_s el2 out3_path_s el1 out3_path_s el0 out3_divider 3 out3_divider 2 out3_divider 1 out3_divider 0
IDT82V3285 wan pl l programming information 120 december 9, 2008 out4_freq_cnfg - output cloc k 4 frequency configuration address:70h type: read / write default value: 00000110 bit name description 7 - 4 out4_path_sel[3:0] these bits select an input to out4. 0000 ~ 0011: the output of t0 apll. (default: 0000) 0100: the output of t0 dpll 77.76 mhz path. 0101: the output of t0 dpll 12e1/24t1/e3/t3 path. 0110: the output of t0 dpll 16e1/16t1 path. 0111: the output of t0 dpll gsm/obsai/16e1/16t1 path. 1000 ~ 1011: the output of t4 apll. 1100: the output of t4 dpll 77.76 mhz path. 1101: the output of t4 dpll 12e1/24t1/e3/t3 path. 1110: the output of t4 dpll 16e1/16t1 path. 1111: the output of t4 dpll gsm/gps/16e1/16t1 path. 3 - 0 out4_divider[3:0] these bits select a division factor of the divider for out4. the output frequency is determined by the division factor and the signal derived from t0/t4 dpll or t0/t4 apll output (selected by the out4_path_sel[3:0] bits (b7~4, 70h)). if the signal is derived from one of the t0/t4 dpll outputs, please refer to table 24 for the division factor selection. if the signal is derived from the t0/t4 apll output, please refer to table 25 for the division factor selection. 76543210 out4_path_s el3 out4_path_s el2 out4_path_s el1 out4_path_s el0 out4_divider 3 out4_divider 2 out4_divider 1 out4_divider 0
IDT82V3285 wan pl l programming information 121 december 9, 2008 out5_freq_cnfg - output cloc k 5 frequency configuration output_inv2 - output clock 4 & 5 invert configuration address:71h type: read / write default value: 00001000 bit name description 7 - 4 out5_path_sel[3:0] these bits select an input to out5. 0000 ~ 0011: the output of t0 apll. (default: 0000) 0100: the output of t0 dpll 77.76 mhz path. 0101: the output of t0 dpll 12e1/24t1/e3/t3 path. 0110: the output of t0 dpll 16e1/16t1 path. 0111: the output of t0 dpll gsm/obsai/16e1/16t1 path. 1000 ~ 1011: the output of t4 apll. 1100: the output of t4 dpll 77.76 mhz path. 1101: the output of t4 dpll 12e1/24t1/e3/t3 path. 1110: the output of t4 dpll 16e1/16t1 path. 1111: the output of t4 dpll gsm/gps/16e1/16t1 path. 3 - 0 out5_divider[3:0] these bits select a division factor of the divider for out5. the output frequency is determined by the division factor and the signal derived from t0/t4 dpll or t0/t4 apll output (selected by the out5_path_sel[3:0] bits (b7~4, 71h)). if the signal is derived from one of the t0/t4 dpll outputs, please refer to table 24 for the division factor selection. if the signal is derived from the t0/t4 apll output, please refer to table 25 for the division factor selection. address:72h type: read / write default value: 01000000 bit name description 7 - 2 - reserved. 1out5_inv this bit determines whether the output on out5 is inverted. 0: not inverted. (default) 1: inverted. 0out4_inv this bit determines whether the output on out4 is inverted. 0: not inverted. (default) 1: inverted. 76543210 out5_path_s el3 out5_path_s el2 out5_path_s el1 out5_path_s el0 out5_divider 3 out5_divider 2 out5_divider 1 out5_divider 0 76543210 - - - - - - out5_inv out4_inv
IDT82V3285 wan pl l programming information 122 december 9, 2008 output_inv1 - output clo ck 1 ~ 3 invert configuration address:73h type: read / write default value: 01000000 bit name description 7 - 5 - reserved. 4out3_inv this bit determines whether the output on out3 is inverted. 0: not inverted. (default) 1: inverted. 3out2_inv this bit determines whether the output on out2 is inverted. 0: not inverted. (default) 1: inverted. 2out1_inv this bit determines whether the output on out1 is inverted. 0: not inverted. (default) 1: inverted. 1 - 0 - reserved. 76543210 - - - out3_inv out2_inv out1_inv - -
IDT82V3285 wan pl l programming information 123 december 9, 2008 fr_mfr_sync_cnfg - frame sync & mult iframe sync output configuration address:74h type: read / write default value: 01100000 bit name description 7 in_2k_4k_8k_inv this bit determines whether the input clock is inverted before locked by the t0/t4 dpll when the input clock is 2 khz, 4 khz or 8 khz. 0: not inverted. (default) 1: inverted. 6 8k_en this bit determines whether an 8 khz signal is enabled to be output on frsync_8k. 0: disabled. frsync_8k outputs low. 1: enabled. (default) 5 2k_en this bit determines whether a 2 khz signal is enabled to be output on mfrsync_2k. 0: disabled. mfrsync_2k outputs low. 1: enabled. (default) 4 2k_8k_pul_position this bit is valid only when frsync_8k and/or mfrsync_2k out put pulse; i.e., when one of the 8k_pul bit (b2, 74h) and the 2k_pul bit (b0, 74h) is ?1? or when the 8k_pul bit (b2, 74h) and the 2k_pul bit (b0, 74h) are both ?1?. it deter- mines the pulse position referring to the standard 50:50 duty cycle. 0: pulsed on the falling edge of the standard 50:50 duty cycle position. (default) 1: pulsed on the rising edge of the standard 50:50 duty cycle position. 38k_inv this bit determines whether the output on frsync_8k is inverted. 0: not inverted. (default) 1: inverted. 2 8k_pul this bit determines whether the output on frsync_8k is 50:50 duty cycle or pulsed. 0: 50:50 duty cycle. (default) 1: pulsed. the pulse width is defined by the period of the output on out1. 12k_inv this bit determines whether the output on mfrsync_2k is inverted. 0: not inverted. (default) 1: inverted. 0 2k_pul this bit determines whether the output on mfrsync_2k is 50:50 duty cycle or pulsed. 0: 50:50 duty cycle. (default) 1: pulsed. the pulse width is defined by the period of the output on out1. 76543210 in_2k_4k_8k_i nv 8k_en 2k_en 2k_8k_pul_p osition 8k_inv 8k_pul 2k_inv 2k_pul
IDT82V3285 wan pl l programming information 124 december 9, 2008 7.2.9 pbo & phase offset control registers phase_mon_pbo_cnfg - phase transi ent monitor & pbo configuration phase_offset[7:0]_cnfg - ph ase offset configuration 1 address:78h type: read / write default value: 0x000110 bit name description 7 in_noise_window this bit determines whether the input clock whose edge respect to the reference clock is outside 5% is enabled to be selected for t0/t4 dpll. 0: disabled. (default) 1: enabled. 6-reserved. 5ph_mon_en this bit is valid only when the ph_mon_pbo_en bit (b4, 78h) is ?1?. it determines whether the phase transient monitor is enabled to monitor the phase-time changes on the t0 selected input clock. 0: disabled. (default) 1: enabled. 4 ph_mon_pbo_en this bit determines whether a pbo event is triggered when the phase-time changes on the t0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds with the ph_mon_en bit being ?1?. the limit is programmed by the ph_tr_mon_limt[3:0] bits (b3~0, 78h). 0: disabled. (default) 1: enabled. 3 - 0 ph_tr_mon_limt[3:0] these bits represent an unsigned integer. the phase transient monitor limit in ns can be calculated as follows: limit (ns) = (ph_tr_mon_limt[3:0] + 7) x 156. address:7ah type: read / write default value: 00000000 bit name description 7 - 0 ph_offset[7:0] refer to the descriptio n of the ph_offset[9:8] bits (b1~0, 7bh). 76543210 in_noise_win dow - ph_mon_en ph_mon_pbo _en ph_tr_mon_l imt3 ph_tr_mon_l imt2 ph_tr_mon_l imt1 ph_tr_mon_l imt0 76543210 ph_offset7 ph_offset6 ph_offset5 ph_offset4 p h_offset3 ph_offset2 p h_offset1 ph_offset0
IDT82V3285 wan pl l programming information 125 december 9, 2008 phase_offset[9:8]_cnfg - ph ase offset configuration 2 address:7bh type: read / write default value: 0xxxxx00 bit name description 7ph_offset_en this bit determines whether the input-to-output phase offset is enabled. if the device is configured as the master, the input-to-output phase offset: 0: disabled. (default) 1: enabled. if the device is configured as the slave, the input-to-output phase offset is always enabled. 6 - 2 - reserved. 1 - 0 ph_offset[9:8] these bits represent a 2?s complement signed integer. if the value is multiplied by 0.61, the input-to-output phase offset in n s to adjust will be gotten. 76543210 ph_offset_e n - - - - - ph_offset9 ph_offset8
IDT82V3285 wan pl l programming information 126 december 9, 2008 7.2.10 synchronization configuration registers sync_monitor_cnfg - sync monitor configuration sync_phase_cnfg - sync phase configuration address:7ch type: read / write default value: x0101011 bit name description 7 - reserved. 6 - 4 sync_mon_limt[2:0] these bits set the limit for the external sync alarm. 000: 1 ui. 001: 2 ui. 010: 3 ui. (default) 011: 4 ui. 100: 5 ui. 101: 6 ui. 110: 7 ui. 111: 8 ui. 3 - 0 - these bits must be set to ?1011?. address:7dh type: read / write default value: xxxxxx00 bit name description 7 - 2 - reserved. 1 - 0 sync_ph1[1:0] these bits set the sampling of ex_sync1 when ex_sync1 is enabled to synchronize the frame sync output signal. nomi- nally, the falling edge of ex_sync1 is aligned with the rising edge of the t0 selected input clock. 00: on target. (default) 01: 0.5 ui early. 10: 1 ui late. 11: 0.5 ui late. 7 6 5 4 3210 - sync_mon_limt2 sync_mon_limt1 sync_mon_limt0 - - - - 76543210 - - - - - - sync_ph11 sync_ph10
IDT82V3285 wan pl l thermal management 127 december 9, 2008 8 thermal management the device operates over the i ndustry temperature range -40c ~ +85c. to ensure the functionality and reliability of the device, the maxi- mum junction temperature t jmax should not exceed 125c. in some applications, the device will consume more power and a thermal solution should be provided to ensure the junction temperature t j does not exceed the t jmax . 8.1 junction temperature junction temperature t j is the temperature of package typically at the geographical center of the chip where t he device's electrical circuits are. it can be calculated as follows: equation 1: t j = t a + p x ja where: ja = junction-to-ambient thermal resistance of the package t j = junction temperature t a = ambient temperature p = device power consumption in order to calculate junction temperature, an appropriate ja must be used. the ja is shown in table 43 . power consumption is the core pow er excluding the power dissipated in the loads. table 42 provides power consumpt ion in special environ- ments. 8.2 example of junction temperature calculation assume: t a = 85c ja = 18.9c/w (tqfp/eqg100 soldered & when airflow rate is 0 m/s) p = 1.9w the junction temperature t j can be calculated as follows: t j = t a + p x ja = 85c + 1.9w x 18.9c/w = 120.9c the junction temperature of 120.9 c is below the maximum junction temperature of 125c so no extra heat enhancement is required. in some operation environments, the calculated junction temperature might exceed the maximum junction temperature of 125c and an exter- nal thermal solution such as a heatsink is required. 8.3 heatsink evaluation a heatsink is expanding the surface area of the device to which it is attached. ja is now a combination of device case and heat-sink thermal resistance, as the heat flowing from the die junction to ambient goes through the package and the heatsink. ja can be calculated as follows: equation 2: ja = jc + ch + ha where: jc = junction-to-case thermal resistance ch = case-to-heatsink thermal resistance ha = heatsink-to-ambient thermal resistance ch + ha determines which heatsink and heatsink attachment can be selected to ensure the junction temperature does not exceed the maximum junction temperature. according to equation 1 and 2, ch + ha can be calculated as follows: equation 3: ch + ha = (t j - t a ) / p - jc assume: t j = 125c (t jmax ) t a = 85c p = 1.9 w jc = 16.1c/w (tqfp/eqg100) ch + ha can be calculated as follows: ch + ha = (125c - 85c ) / 1.9w - 16.1c/w = 5.0c/w that is, if a heatsink and heatsink attachment whose ch + ha is below or equal to 5.0c/w is used in such operation environment, the junction temperature will not exc eed the maximum junction temperature. table 42: power consumption an d maximum junction temperature package power consumption (w) operating voltage (v) t a (c) maximum junction temperature (c) tqfp/pn100 1.9 3.6 85 125 tqfp/eqg100 1.9 3.6 85 125 table 43: thermal data package pin count thermal pad jc (c/w) jb (c/w) ja (c/w) vs air flow in m/s 012345 tqfp/pn100 100 no 11.0 34.2 39.3 36.2 34.3 33.5 32.9 32.6 tqfp/eqg100 100 yes/exposed 16.1 34.2 35.8 31.1 29.5 28.6 27.9 27.4 tqfp/eqg100 100 yes/soldered* 16.1 1.3 18.9 14.6 13.5 12.9 12.6 12.4 *note: simulated with 3 x 3 array of thermal vias.
IDT82V3285 wan pl l thermal management 128 december 9, 2008 8.4 tqfp epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corre- sponding to the exposed metal pad or exposed heat slug on the pack- age, as shown in figure 27 . the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electri- cal performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. figure 27. assembly for expose pad thermal release path (side view) while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conduc tivity require- ments. thus, thermal and electrical analysis and/or testing are recom- mended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorpo- rated in the land pattern. it is recommended to use as many vias con- nected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1 oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guide- line only. for further information, please refer to the application note on the surface mount assembly of am kor?s thermally/electrically enhance leadfame base package, amkor technology. pin pin thermal via solder ground plane land pattern (ground pad) pin pad solder exposed heat slug pin pad solder
IDT82V3285 wan pl l electrical specifications 129 december 9, 2008 9 electrical specifications 9.1 absolute maximum rating 9.2 recommended oper ation conditions table 44: absolute maximum rating symbol parameter min max unit v dd supply voltage vdd -0.5 3.6 v v in input voltage (non-supply pins) 5.5 v v out output voltage (non-supply pins) 5.5 v t a ambient operating temperature range -40 +85 c t stor storage temperature -50 +150 c table 45: recommended operation conditions symbol parameter min typ max unit test condition v dd power supply (dc voltage) vdd 3.0 3.3 3.6 v t a ambient temperature range -40 +85 c i dd supply current 455 528 ma exclude the loading current and power p tot total power dissipation 1.5 1.9 w
IDT82V3285 wan pl l electrical specifications 130 december 9, 2008 9.3 i/o specifications 9.3.1 cmos input / output port from table 46 to table 49 , v dd is 3.3 v. table 46: cmos input port electrical characteristics parameter description min typ max unit test condition v ih input voltage high 0.7v dd v v il input voltage low 0.2v dd v i in input current 10 a v in input voltage -0.5 5.5 v table 47: cmos input port wi th internal pull-up resist or electrical characteristics parameter description min typ max unit test condition v ih input voltage high 0.7v dd v v il input voltage low 0.2v dd v p u pull-up resistor 10 80 k ? i in input current 250 a v in input voltage -0.5 5.5 v table 48: cmos input port wi th internal pull-down resist or electrical characteristics parameter description min typ max unit test condition v ih input voltage high 0.7v dd v v il input voltage low 0.2v dd v p d pull-down resistor 10 80 k ? other cmos input port with internal pull-down resistor 540 trst and tck pin 100 300 a[6:0], ad[7:0] pins i in input current 350 a other cmos input port with internal pull-down resistor 700 trst and tck pin 40 a[6:0], ad[7:0] pins v in input voltage -0.5 5.5 v table 49: cmos output port electrical characteristics application pin parameter description min typ max unit test condition output clock v oh output voltage high 2.4 v dd v i oh = 8 ma v ol output voltage low 0 0.4 v i ol = 8 ma t r rise time 3 4 ns 15 pf t f fall time 3 4 ns 15 pf other output v oh output voltage high 2.5 v dd v i oh = 4 ma v ol output voltage low 0 0.4 v i ol = 4 ma t r rise time 10 ns 50 pf t f fall time 10 ns 50 pf
IDT82V3285 wan pl l electrical specifications 131 december 9, 2008 9.3.2 pecl / lvds input / output port 9.3.2.1 pecl input / output port figure 28. recommended pecl input port line termi- nation figure 29. recommended pecl output port line ter- mination in3_pos in3_neg in4_pos in4_neg 2 khz to 667 mhz 50 ? (transmission line) v dd (+ 3.3 v) 130 ? 82 ? gnd v dd (+ 3.3 v) 130 ? 82 ? gnd 50 ? (transmission line) 50 ? (transmission line) v dd (+ 3.3 v) 130 ? 82 ? gnd v dd (+ 3.3 v) 130 ? 82 ? gnd 50 ? (transmission line) 2 khz to 667 mhz v dd (+ 3.3 v) 130 ? 82 ? out4_pos out4_neg out5_pos out5_neg 2 khz to 667 mhz 50 ? (transmission line) 50 ? (transmission line) gnd v dd (+ 3.3 v) 130 ? 82 ? gnd v dd (+ 3.3 v) 130 ? 82 ? 2 khz to 667 mhz 50 ? (transmission line) 50 ? (transmission line) gnd v dd (+ 3.3 v) 130 ? 82 ? gnd
IDT82V3285 wan pl l electrical specifications 132 december 9, 2008 table 50: pecl input / output port electrical characteristics parameter description min typ max unit test condition v il input low voltage, differential inputs 1 v dd - 2.5 v dd - 0.5 v v ih input high voltage, differential inputs 1 v dd - 2.4 v dd - 0.4 v v id input differential voltage 0.1 1.4 v v il_s input low voltage, single-ended input 2 v dd - 2.4 v dd - 1.5 v v ih_s input high voltage, single-ended input 2 v dd - 1.3 v dd - 0.5 v i ih input high current, input differential voltage v id = 1.4 v -10 10 a i il input low current, input differential voltage v id = 1.4 v -10 10 a v ol output voltage low 3 v dd - 2.1 v dd - 1.62 v v oh output voltage high 3 v dd - 1.25 v dd - 0.88 v v od output differential voltage 3 580 900 mv t rise output rise time (20% to 80%) 200 300 ps t fall output fall time (20% to 80%) 200 300 ps t skew output differential skew 50 ps note: 1. assuming a differential input voltage of at least 100 mv. 2. unused differential input terminated to v dd -1.4 v. 3. with 50 ? load on each pin to v dd -2 v, i.e. 82 ? to gnd and 130 ? to v dd .
IDT82V3285 wan pl l electrical specifications 133 december 9, 2008 9.3.2.2 lvds input / output port figure 30. recommended lvds input port line termi- nation figure 31. recommended lvds output port line ter- mination in3_pos in3_neg in4_pos in4_neg 50 ? (transmission line) 100 ? 2 khz to 667 mhz 100 ? 2 khz to 667 mhz 50 ? (transmission line) 50 ? (transmission line) 50 ? (transmission line) out4_pos out4_neg out5_pos out5_neg 100 ? 100 ? 2 khz to 667 mhz 2 khz to 667 mhz 50 ? (transmission line) 50 ? (transmission line) 50 ? (transmission line) 50 ? (transmission line) table 51: lvds input / output port electrical characteristics parameter description min typ max unit test condition v cm input common-mode voltage range 0 1200 2400 mv v diff input peak differential voltage 100 900 mv v idth input differential threshold -100 100 mv r term external differential termination impedance 95 100 105 ? v oh output voltage high 1350 1475 mv r load = 100 ? 1% v ol output voltage low 925 1100 mv r load = 100 ? 1% v od differential output voltage 250 400 mv r load = 100 ? 1% v os output offset voltage 1125 1275 mv r load = 100 ? 1% r o differential output impedance 80 100 120 ? v cm = 1.0 v or 1.4 v ? r o r o mismatch between a and b 20 % v cm = 1.0 v or 1.4 v ? v od change in v od between logic 0 and logic 1 25 mv r load = 100 ? 1% ? v os change in v os between logic 0 and logic 1 25 mv r load = 100 ? 1% i sa , i sb output current 24 ma driver shorted to gnd i sab output current 12 ma driver shorted together t rise output rise time (20% to 80%) 200 300 ps r load = 100 ? 1% t fall output fall time (20% to 80%) 200 300 ps r load = 100 ? 1% t skew output differential skew 50 ps r load = 100 ? 1%
IDT82V3285 wan pl l electrical specifications 134 december 9, 2008 9.4 jitter & wander performance table 52: output clock jitter generation test definition 1 peak to peak typ rms typ note test filter n x 2.048mhz without apll <2 ns <200 ps 20 hz - 100 khz n x 2.048mhz with t0/t4 apll <1 ns <100 ps see table 53: output clock phase noise for details 20 hz - 100 khz n x 1.544 mhz without apll <2 ns <200 ps 10 hz - 40 khz n x 1.544 mhz with t0/t4 apll <1 ns <100 ps see table 53: output clock phase noise for details 10 hz - 40 khz 44.736 mhz without apll <2 ns <200 ps see table 53: output clock phase noise for details 100 hz - 800 khz 44.736 mhz with t0/t4 apll <1 ns <100 ps 100 hz - 800 khz 34.368 mhz without apll <2 ns <200 ps see table 53: output clock phase noise for details 10 hz - 400 khz 34.368 mhz with t0/t4 apll <1 ns <100 ps 10 hz - 400 khz oc-3 (chip t0 dpll + t0/t4 apll) 6.48 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz, 155.52 mhz, 311.04 mhz, 622.08 mhz output 0.004 ui p-p 0.001 ui rms gr-253, g.813 option 2 limit 0.1 ui p-p (1 ui-6430 ps) 12 khz - 1.3 mhz 0.004 ui p-p 0.001 ui rms g.813 option 1, g.812 limit 0.5 ui p-p (1 ui-6430 ps) 500 hz - 1.3 mhz 0.001 ui p-p 0.001 ui rms g.813 option 1 limit 0.1 ui p-p (1 ui-6430 ps) 65 khz - 1.3 mhz oc-12 (chip t0 dpll + t0/t4 apll) 6.48 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz, 155.52 mhz, 311.04 mhz, 622.08 mhz output + intel gd16523 + optical transceiver) 0.018 ui p-p 0.007 ui rms gr-253, g.813 option 2 limit 0.1 ui p-p (1 ui-1608 ps) 12 khz - 5 mhz 0.028 ui p-p 0.009 ui rms g.813 option 1, g.812 limit 0.5 ui p-p (1 ui-1608 ps) 1 khz - 5 mhz 0.002 ui p-p 0.001 ui rms g.813 option 1, g.812 limit 0.1 ui p-p (1 ui-160 8ps) 250 khz - 5 mhz stm-16 (chip t0 dpll + t0/t4 apll) 6.48 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz, 155.52 mhz, 311.04 mhz, 622.08 mhz output + intel gd16523 + optical transceiver) 0.162 ui p-p 0.03 ui rms g.813 option 1, g.812 limit 0.5 ui p-p (1 ui-402 ps) 5 khz - 20 mhz 0.01 ui p-p 0.009 ui rms g.813 option 1, g.812 limit 0.1 ui p-p (1 ui-402 ps) 1 mhz - 20 mhz note: 1. cmac e2747 tcxo is used.
IDT82V3285 wan pl l electrical specifications 135 december 9, 2008 table 53: output clock phase noise output clock 1 @100hz offset typ @1khz offset typ @10khz offset typ @100khz offset typ @1mhz offset typ @5mhz offset typ unit 622.08 mhz (t0 dpll + t0/t4 apll) -70 -86 -95 -100 -107 -128 dbc/hz 155.52 mhz (t0 dpll + t0/t4 apll) -82 -98 -107 -112 -119 -140 dbc/hz 38.88 mhz (t0 dpll + t0/t4 apll) -94 -110 -118 -124 -131 -143 dbc/hz 16e1 (t0/t4 apll) -94 -110 -118 -125 -131 -142 dbc/hz 16t1 (t0/t4 apll) -95 -112 -120 -127 -132 -143 dbc/hz e3 (t0/t4 apll) -93 -109 -116 -124 -131 -138 dbc/hz t3 (t0/t4 apll) -92 -108 -116 -122 -126 -141 dbc/hz note: 1. cmac e2747 tcxo is used. table 54: input jitter tolerance (155.52 mhz) jitter frequency jitter tolerance amplitude (ui p-p) 12 hz > 2800 178 hz > 2800 1.6 mhz > 311 15.6 mhz > 311 0.125 hz > 39 19.3 hz > 39 500 hz > 1.5 6.5 khz > 1.5 65 khz > 0.15 1.3 mhz > 0.15 table 55: input jitter tolerance (1.544 mhz) jitter frequency jitter tolerance amplitude (ui p-p) 1 hz 150 5 hz 140 20 hz 130 300 hz 38 400 hz 25 700 hz 15 2400 hz 5 10 khz 1.2 40 khz 0.5 table 56: input jitter tolerance (2.048 mhz) jitter frequency jitter tolerance amplitude (ui p-p) 1 hz 150 5 hz 140 20 hz 130 300 hz 40 400 hz 33 700 hz 18 2400 hz 5.5 10 khz 1.3 50 khz 0.4 100 khz 0.4 table 57: input jitter tolerance (8 khz) jitter frequency jitter tolerance amplitude (ui p-p) 1 hz 0.8 5 hz 0.7 20 hz 0.6 300 hz 0.16 400 hz 0.14 700 hz 0.07 2400 hz 0.02 3600 hz 0.01
IDT82V3285 wan pl l electrical specifications 136 december 9, 2008 table 58: t0 dpll jitter transfer & damping factor 3 db bandwidth programmable damping factor 0.5 mhz 1.2, 2.5, 5, 10, 20 1 mhz 1.2, 2.5, 5, 10, 20 2 mhz 1.2, 2.5, 5, 10, 20 4 mhz 1.2, 2.5, 5, 10, 20 8 mhz 1.2, 2.5, 5, 10, 20 15 mhz 1.2, 2.5, 5, 10, 20 30 mhz 1.2, 2.5, 5, 10, 20 60 mhz 1.2, 2.5, 5, 10, 20 0.1 hz 1.2, 2.5, 5, 10, 20 0.3 hz 1.2, 2.5, 5, 10, 20 0.6 hz 1.2, 2.5, 5, 10, 20 1.2 hz 1.2, 2.5, 5, 10, 20 2.5 hz 1.2, 2.5, 5, 10, 20 4 hz 1.2, 2.5, 5, 10, 20 8 hz 1.2, 2.5, 5, 10, 20 18 hz 1.2, 2.5, 5, 10, 20 35 hz 1.2, 2.5, 5, 10, 20 70 hz 1.2, 2.5, 5, 10, 20 560 hz 1.2, 2.5, 5, 10, 20 table 59: t4 dpll jitter transfer & damping factor 3 db bandwidth programmable damping factor 18 hz 1.2, 2.5, 5, 10, 20 35 hz 1.2, 2.5, 5, 10, 20 70 hz 1.2, 2.5, 5, 10, 20 560 hz 1.2, 2.5, 5, 10, 20
IDT82V3285 wan pl l electrical specifications 137 december 9, 2008 9.5 output wander generation figure 32. output wander generation template tested result template tested result
IDT82V3285 wan pl l electrical specifications 138 december 9, 2008 9.6 input / output clock timing the inputs and outputs are aligned ideally. but due to the circ uit delays, there is delay between the inputs and outputs. figure 33. input / output clock timing table 60: input/outp ut clock timing 3 symbol typical delay 1 (ns) peak to peak delay variation 2 (ns) t 1 41.6 t 2 11.6 t 3 11.6 t 4 21.6 t 5 1.4 1.6 t 6 31.6 note: 1. typical delay provided as reference only. 2. ?peak to peak delay variation? is th e delay variation that is g uaranteed not to be exceeded for in5 in master/slave operati on. 3. tested when in5 is selected. 8 khz input clock 8 khz output clock 6.48 mhz input clock 6.48 mhz output clock 19.44 mhz input clock 19.44 mhz output clock 25.92 mhz input clock 25.92 mhz output clock 38.88 mhz input clock 38.88 mhz output clock 51.84 mhz input clock 51.84 mhz output clock t 1 t 2 t 3 t 4 t 5 t 6
IDT82V3285 wan pl l electrical specifications 139 december 9, 2008 9.7 output clock timing figure 34. output clock timing table 61: output clock timing symbol typical delay (ns) peak to peak delay variation (ns) t 1 02 t 2 02 t 3 02 t 4 02 t 5 02 t 6 02 t 7 02 t 8 02 t 9 02 t 10 02 t 11 01.5 t 12 0 1.5 (not recommended to use) t 13 0 1.5 (not recommended to use) n x t1 (1.544 mhz) t 1 n x e1 (2.048 mhz) e3 (34.368 mhz) 6.48 mhz 19.44 mhz 25.92 mhz 38.88 mhz 51.84 mhz 77.76 mhz 155.52 mhz 311.04 mhz 622.08 mhz mfrsync_2k/ frsync_8k t3 (44.736 mhz) t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13
glossary 140 december 9, 2008 3g --- third generation adsl --- asymmetric digital subscriber line apll --- analog phase locked loop atm --- asynchronous transfer mode bits --- building integrated timing supply cmos --- complementary metal-oxide semiconductor dco --- digital controlled oscillator dpll --- digital phase locked loop dsl --- digital subscriber line dslam --- digital subscriber line access mux dwdm --- dense wavelength division multiplexing eprom --- erasable programmable read only memory gps --- global positioning system gsm --- global system for mobile communications iir --- infinite impulse response ip --- internet protocol isdn --- integrated services digital network jtag --- joint test action group lpf --- low pass filter lvds --- low voltage differential signal mtie --- maximum time interval error mux --- multiplexer obsai --- open base station architecture initiative oc-n --- optical carried rate, n = 1, 3, 12, 48, 192, 768; 51 mbi t/s, 155 mbit/s, 622 mb it/s, 2.5 gbit/s, 10 gbit/s, 40 gbit/s. pbo --- phase build-out pdh --- plesiochronous digital hierarchy glossary
glossary 141 december 9, 2008 IDT82V3285 wan pl l pecl --- positive emitte r coupled logic pfd --- phase & frequency detector pll --- phase locked loop rms --- root mean square prs --- primary reference source sdh --- synchronous digital hierarchy sec --- sdh / sonet equipment clock smc --- sonet minimum clock sonet --- synchronous optical network ssu --- synchronization supply unit stm --- synchronous transfer mode tcm-isdn --- time compression multiplexing integrated services digital network tdev --- time deviation ui --- unit interval wll --- wireless local loop
index 142 december 9, 2008 a averaged phase error ........................................................................ 32 b bandwidths and damping factors ..................................................... 32 acquisition bandwidth and damping factor ............................... 32 locked bandwidth and damping factor ..................................... 32 starting bandwidth and damping factor .................................... 32 c calibration .......................................................................................... 18 coarse phase loss ............................................................................ 25 crystal oscillator ................................................................................ 18 current frequency offset ................................................................... 32 d dco ................................................................................................... 32 division factor .................................................................................... 20 dpll hard alarm ............................................................................... 25 dpll hard limit ................................................................................. 25 dpll operating mode ................................................................. 32 , 33 free-run mode ................................................................... 32 , 33 holdover mode .................................................................... 32 , 33 automatic fast averaged ................................................... 33 automatic instantaneous .................................................... 33 automatic slow averaged .................................................. 33 manual ................................................................................ 33 locked mode ....................................................................... 32 , 33 temp-holdover mode ......................................................... 32 lost-phase mode ....................................................................... 32 pre-locked mode ....................................................................... 32 pre-locked2 mode ..................................................................... 33 dpll soft alarm ................................................................................. 25 dpll soft limit .................................................................................. 25 e external sync alarm ........................................................................... 39 f fast loss ............................................................................................ 25 fine phase loss ................................................................................. 25 frequency hard alarm .................................................................22 , 27 frequency hard alarm threshold ...................................................... 22 h hard limit ........................................................................................... 25 holdover frequency offset ................................................................ 33 i iir ...................................................................................................... 33 input clock frequency ....................................................................... 22 input clock selection ......................................................................... 23 automatic selection ..............................................................24 , 27 external fast selection .........................................................23 , 27 forced selection ...................................................................24 , 27 internal leaky bucket accumulator ................................................... 21 bucket size ................................................................................ 21 decay rate ................................................................................ 21 lower threshold ........................................................................ 21 upper threshold ........................................................................ 21 l limit ................................................................................................... 35 lpf .................................................................................................... 32 m master / slave application ................................................................. 44 master / slave configuration .............................................................. 41 master clock ...................................................................................... 18 microprocessor interface ................................................................... 45 microprocessor interface eprom ...................................................................................... 46 intel ............................................................................................ 49 motorola ..................................................................................... 51 multiplexed ................................................................................. 47 serial .......................................................................................... 53 n no-activity alarm ..........................................................................21 , 27 p pbo ................................................................................................... 35 index
index 143 december 9, 2008 IDT82V3285 wan pl l pfd .................................................................................................... 32 phase lock alarm ....................................................................... 26 , 27 phase offset ....................................................................................... 35 phase-compared ......................................................................... 25 , 35 phase-time ......................................................................................... 35 pre-divider ......................................................................................... 20 divn divider ................................................................................ 20 hf divider ................................................................................... 20 lock 8k divider ........................................................................... 20 r reference clock ................................................................................ 22 s selected input clock switch .............................................................. 27 non-revertive switch ................................................................. 28 revertive switch ......................................................................... 27 state machine ..............................................................................29 , 31 v validity ............................................................................................... 27
IDT82V3285 wan pl l 144 december 9, 2008 package dimensions figure 35. 100-pin eqg package dimensions (a) (in millimeters)
IDT82V3285 wan pl l 145 december 9, 2008 figure 36. 100-pin eqg package di mensions (b) (in millimeters)
IDT82V3285 wan pl l 146 december 9, 2008 figure 37. eqg100 recommended land patt ern with exposed pad (in millimeters)
IDT82V3285 wan pll corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com for sales: 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 for tech support: 408-360-1552 email:telecomhelp@idt.com idt and the idt logo are trademarks of integrated device technology, inc. 147 ordering information datasheet document history 12/09/2008 pgs. 127, 128, 129, 134, 144, 145, 146, 147 xxxxxxx xx x device type blank process/ temperature range 82v3285 industrial (-40 c to +85 c) wan pll pf thin quad flatpack (tqfp, pn100) pfg green thin quad flatpack (tqfp, png100) eqg green thin quad flatpack (tqfp, eqg100)

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